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參數(shù)資料
| 型號： | TNETA1600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| 中文描述： | SONET / SDH的自動(dòng)柜員機(jī)接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動(dòng)柜員機(jī)接收器/傳送器） |
| 文件頁數(shù)： | 25/54頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | TNETA1600 |
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TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
control registers
The control registers are located at addresses 007 to 00B (hex). The control registers provide a means of
controlling the operation of the device through the controller interface. A reset operation, initiated either by taking
RESET active (low) or by performing a write operation to the ID register, clears the control registers. The bit
definitions for the control registers are shown in Table 6. Several of the modes shown are test modes. These
modes may not be suitable for normal use of the device as they may enable or disable receive and/or transmit
functions of the device.
Table 6. Coding for Control Registers
ACTION
CONTROL
REGISTER 1
(ADDRESS 007)
CONTROL
REGISTER 2
(ADDRESS 008)
CONTROL
REGISTER 3
(ADDRESS 009)
CONTROL
REGISTER 4
(ADDRESS 00A)
CONTROL
REGISTER 5
(ADDRESS 00B)
Disable-error correction for receive
ATM-cell headers
xxxx xxx1
–
–
–
–
Disable-transmit ATM-cell header
HEC-byte generation
Enable-terminal loopback (TLB)
xxxx xx1x
–
–
–
–
xxxx x1xx
–
–
–
–
Enable-facility loopback (FLB) output
xxxx 1xxx
–
–
–
–
Disable the dropping of ATM cells with
multiple-bit header errors
xxx1 xxxx
–
–
–
–
Disable the dropping of ATM idle cells
from the receive data stream
Disable the dropping of ATM unassigned
cells from the receive data stream
Not implemented
xx1x xxxx
–
–
–
–
x1xx xxxx
–
–
–
–
1xxx xxxx
–
–
–
–
Enable-clock-loop output
–
xxxx xxx1
–
–
–
Transmit ATM unassigned cells as filler
–
xxxx xx1x
–
–
–
Place transmit-overhead RAM in
program mode
–
xxxx x1xx
–
–
–
Cell-interface 16-bit alternate-data
format
–
xxxx 1xxx
–
–
–
Force-transmit line AIS
–
xxx1 xxxx
–
–
–
Force-transmit line FERF
–
xx1x xxxx
–
–
–
Force-transmit path FERF
–
x1xx xxxx
–
–
–
Enable LOCA to path RDI soak count
–
1xxx xxxx
–
–
–
Force-transmit path AIS
–
–
xxxx xxx1
–
–
Disable receive SONET descrambler
–
–
xxxx xx1x
–
–
Disable receive ATM descrambler
–
–
xxxx x1xx
–
–
Disable transmit SONET scrambler
–
–
xxxx 1xxx
–
–
Disable transmit ATM scrambler
–
–
xxx1 xxxx
–
–
Enable short-frame-test mode
–
–
xx1x xxxx
–
–
Enable increment-counter-test mode
–
–
x1xx xxxx
–
–
Enable RAM-access-test mode
–
–
1xxx xxxx
–
–
Enable UTOPIA-loopback-test mode
–
–
–
xxxx xxx1
–
Force-transmit path RDI – 01
–
–
–
xxxx xx1x
–
Force-transmit path RDI – 10
–
–
–
xxxx x1xx
–
P
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