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參數(shù)資料
| 型號： | TNETA1600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| 中文描述： | SONET / SDH的自動柜員機接收器/發(fā)送器為622.08，麻省理工學院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動柜員機接收器/傳送器） |
| 文件頁數(shù)： | 29/54頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | TNETA1600 |
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TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
29
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
disable transmit
ATM scrambler
This bit is logically ORed with the TEST3 terminal. If either or both are set to a high level, ATM scrambling
(x
43
+ 1) in the transmitter is disabled. When a reset operation is performed, this bit is cleared (set to 0). The
normal operating state of the TNETA1600 is to provide ATM scrambling in the transmitter; an action must be
taken to disable this function.
enable short-frame test mode
This bit is logically ORed with the TEST0 terminal. If either or both are set to a high level, the short-frame test
mode is enabled. This causes the receive side to support frames consisting of 36 bytes of TOH and 84 bytes
of SPE per row at 622.08 Mbit/s or 9 bytes of TOH and 21 bytes of SPE per row at 155.52 Mbit/s. Normal receive
operation is also supported in this mode, including pointer processing only to the extent of valid J1 locations.
When a reset operation is performed, this bit is cleared (set to 0). The normal operation state of the TNETA1600
is to support only normal frames, not shortened frames.
enable increment-counter test mode
When set to a high level, this bit causes all counters to be incremented by internal clocks without the occurrence
of the associated conditions. The internal clocks used for this operation are derived from RPCK. When this mode
is enabled, all block-error and ATM-cell counters are incremented by one on every two rising edges of RPCK.
All coding-violation and FEBE counters are incremented by one on every four rising edges of RPCK. This allows
the counters to be exercised without repeatedly generating the associated conditions. When a reset operation
is performed, this bit is cleared (set to 0). The normal operating state of the TNETA1600 is to support counter
increments only upon the occurrence of the associated condition.
enable RAM-access test mode
When set to a high level, this bit causes the controller interface to enter a special RAM-access mode. In this
mode, read and write access to transmit- and receive-overhead RAM are provided through the controller
interface. Internal access to the RAM is disabled. Consequently, transmit and receive circuitry is nonfunctional.
When this mode is exited, the transmit side resets and default-overhead values are written to RAM. When a
reset operation is performed, this bit is cleared (set to 0). The normal operating state of the TNETA1600 is to
support the internal access to the RAM required for transmit and receive operations.
enable UTOPIA-loopback test mode
This bit is logically ORed with the TEST5 terminal. If either or both are set to a high level, a UTOPIA-loopback
mode is enabled where ATM cells in the receiver are looped back from the receive-cell-interface FIFO output
to the transmit-cell-interface FIFO input where they propagate through the transmit path. The transmit-input
FIFO frequency is still set by TCKI, to avoid the loss of cells looped from the receiver to the transmitter. RCKI
and TCKI must have the same frequency. When a reset operation is performed, this bit is cleared (set to 0). The
normal operating state of the TNETA1600 is to disable this loopback capability.
force-transmit path RDI -01
When set to high level, this bit forces the transmission of a 0 in bit 5 and a 1 in bit 6 of the transmit G1 byte. When
this bit is low, normal processing occurs such that the value inserted in bits 5 and 6 of the G1 byte follows,
provided that they are not otherwise altered through the controller interface. When a reset operation is
performed, this bit is cleared (set to 0).
force transmit path RDI -10
When set to a high level, this bit forces the transmission of a 1 in bit 5 and a 0 in bit 6 of the transmit G1 byte.
When this bit is low, normal processing occurs such that the value inserted in bits 5 and 6 of the G1 byte follows,
provided that they are not otherwise altered through the controller interface. When a reset operation is
performed, this bit is cleared (set to 0).
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PDF描述 |
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| TNETA1610 | STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器) |
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| TNETA1630 | 622.08-MHz Clock-Recovery Device(622.08-MHz時鐘發(fā)生裝置) |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TNETA1600PCM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET FRAMER|QFP|160PIN|PLASTIC |
| TNETA1611PCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Transceiver |
| TNETA1622 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:622.08-MHz CLOCK-RECOVERY DEVICE |
| TNETA1622DW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock/Data Recovery |
| TNETA1630DW | 制造商:Texas Instruments 功能描述: |
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