參數(shù)資料
型號(hào)： TNETA1600
廠商： Texas Instruments, Inc.
英文描述： SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器)
中文描述： SONET / SDH的自動(dòng)柜員機(jī)接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動(dòng)柜員機(jī)接收器/傳送器）
文件頁數(shù)： 20/54頁
文件大小： 1120K
代理商： TNETA1600
TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
B1/B2/B3 parity error, B1/B2/B3 block error-counter overflow, B1/B2/B3 CV-counter overflow
The status bits for these errors indicate that the specified error condition has occurred. The status bits in the
status registers for these conditions are set when the error condition occurs and remain set until the status
register is read. If a B1, B2, or B3 parity error is detected on an incoming frame, the corresponding status bit
is set in the status register, the INTR output goes active, and the status bit remains set until a read of the status
register occurs. Once a read of the status register occurs, the status bit for the error condition is cleared until
the next error condition is detected. A software or hardware reset causes these bits to clear.
loss-of-cell alignment (LOCA)
This bit is set when the device cannot find valid ATM headers in seven consecutive cell slots. This bit is cleared
when the device detects valid ATM headers in seven consecutive cell slots. A hardware or software reset causes
this bit to set. When the logic in the TNETA1600 detects that the LOCA condition has cleared, the status bit in
the status register is cleared. A change in the status bit causes INTR to go active. When the status bit makes
a low-to-high transition, the INTR output goes active. The INTR output also goes active when the status bit
makes a high-to-low transition. Reading the status register does not clear the status bit for this alarm. However,
the INTR output goes inactive on a read of any of the status registers.
loss-of-incoming signal (LOS)
This bit is set when no signal transitions are detected on the incoming data signal for 3.2
μ
s. LOS is cleared when
the device detects two valid SONET/SDH framing patterns without an intervening period (3.2
μ
s or longer)
without signal transitions. The LOS is set as long as the LOS condition exists. When the logic in the TNETA1600
detects that the LOS condition has cleared, the status bit in the status register is cleared. A change in the status
bit causes the INTR output to go active. When the status bit makes a low-to-high transition, the INTR output
goes active. The INTR output also goes active when the status bit makes a high-to-low transition. Reading the
status register does not clear the status bit for this alarm. However, the INTR output goes inactive on a read
of any of the status registers. A software or hardware reset causes this bit to clear.
out of frame (OOF)
This bit is set when the device cannot find a valid SONET/SDH framing pattern in four consecutive frames. OOF
is cleared when the device detects a valid SONET/SDH framing pattern in two consecutive frames. A hardware
or software reset causes this bit to set. This bit is set as long as the OOF condition exists. When the logic in the
TNETA1600 detects that the OOF condition is cleared, the status bit in the status register is cleared. A change
in the status bit causes the INTR output to go active. When the status bit makes a low-to-high transition, the
INTR output goes active. The INTR output also goes active when the status bit makes a high-to-low transition.
Reading the status register does not clear the status bit for this alarm. However, the INTR output goes inactive
on a read of any of the status registers.
loss of frame (LOF)
This bit is set when an OOF condition persists for 3 ms (24 frames). LOF is cleared 1 ms after the OOF condition
clears, if the OOF condition does not reappear in that 1-ms time period. A hardware or software reset causes
this bit to set. This bit is set as long as the LOF condition exists. When the logic in the TNETA1600 detects that
the LOF condition is cleared, the status bit in the status register is cleared. A change in the status bit causes
the INTR output to go active. When the status bit makes a low-to-high transition, the INTR output goes active.
The INTR output also goes active when the status bit makes a high-to-low transition. Reading the status register
does not clear the status bit for this alarm. However, the INTR output goes inactive on a read of any of the status
registers.
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