參數(shù)資料
型號(hào)： TNETA1600
廠商： Texas Instruments, Inc.
英文描述： SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器)
中文描述： SONET / SDH的自動(dòng)柜員機(jī)接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動(dòng)柜員機(jī)接收器/傳送器）
文件頁數(shù)： 22/54頁
文件大小： 1120K
代理商： TNETA1600
TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
loss of pointer (LOP)
This bit is set when the device detects an invalid pointer for eight consecutive frames in the H1 and H2 bytes
of the incoming frame. This bit also is set if a new-data flag (NDF) is detected in eight consecutive frames. This
bit is cleared when a valid pointer with a normal NDF is detected in three consecutive frames or a PAIS condition
is detected. The decoding of NDF is performed by majority voting (i.e., the NDF is detected as being set if three
or four of the bits match the 1001 code). A hardware or software reset causes this bit to clear. This bit is set as
long as the LOP condition exists. When the logic in the TNETA1600 detects that the LOP condition has cleared,
the status bit in the status register is cleared. A change in the status bit causes the INTR output to go active.
When the status bit makes a low-to-high transition, the INTR output goes active. The INTR output also goes
active when the status bit makes a high-to-low transition. Reading the status register does not clear the status
bit for this alarm. However, the INTR output goes inactive on a read of any status register.
path alarm-indication signal (PAIS)
This bit is set when the device receives three consecutive frames with the H1 and H2 bytes set to all ones. This
bit is cleared when the device receives three consecutive frames with a valid pointer in bytes H1 and H2 with
the NDF set to 0110 or when a valid pointer is observed with NDF set to 1001. The decoding of the NDF is
performed by majority voting (i.e., the NDF is detected as being set if three or four of the bits match the 1001
code). A hardware or software reset causes this bit to clear. This bit is set as long as the PAIS condition exists.
When the logic in the TNETA1600 detects that the PAIS conditions has cleared, the status bit in the status
register is cleared. A change in the status bit causes the INTR output to go active. When the status bit makes
a low-to-high transition, the INTR output goes active. The INTR output also goes active when the status bit
makes a high-to-low transition. Reading the status register does not clear the status bit for this alarm. However,
the INTR output goes inactive on a read of any of the status registers.
path remote-defect indicator (PRDI)
This bit is set when the PRDI activation counter reaches a programmable value (one to fifteen) representing
the number of consecutive frames in which the condition occurs. The bit is cleared when the PRDI deactivation
counter reaches an independently programmable value (one to fifteen) representing the number of consecutive
frames occurring without the condition. The PRDI condition is detected by the counters as a one in bit five or
bit six (or both) of the G1 byte. A hardware or software reset causes this bit to clear. This bit is set as long as
the PRDI condition exists. When the logic in the TNETA1600 detects that the PRDI condition has cleared, the
status bit in the status register is cleared. A change in the status bit causes the INTR output to go active. When
the status bit makes a low-to-high transition, the INTR output goes active. The INTR output also goes active
when the status bit makes a high-to-low transition. Reading the status register does not clear the status bit for
this alarm. However, the INTR output goes inactive on a read of any of the status registers.
path far-end receive failure (PFERF)
This bit is set when the device receives a frame with bits 1–4 of the G1 byte set to 1001. This bit is cleared when
the device receives a frame with bits 1–4 of the G1 byte set to any pattern other than 1001. A hardware or
software reset causes this bit to clear. This bit is set as long as the PFERF condition exists. When the logic in
the TNETA1600 detects that the PFERF condition has cleared, the status bit in the status register is cleared.
A change in the status bit causes INTR output to go active. When the status bit makes a low-to-high transition,
the INTR output goes active. The INTR output also goes active when the status bit makes a high-to-low
transition. Reading the status register does not clear the status bit for this alarm. However, the INTR output goes
inactive on a read of any of the status registers.
line FEBE-counter overflow
This status bit indicates that the line FEBE counter has rolled over because of counter overflow. The INTR output
goes active and this bit is set when the counter overflows.
P
相關(guān)PDF資料
PDF描述
TNETA1610 STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器)
TNETA1611 STS-12c/STM-4 Receiver/Transimitter(STS-12C/STM-4接收/傳送器)
TNETA1630 622.08-MHz Clock-Recovery Device(622.08-MHz時(shí)鐘發(fā)生裝置)
TO-252 TO-252 (MP-3Z)
TODX2402 FIBER OPTIC TRANSCEIVING MODULE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TNETA1600PCM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET FRAMER|QFP|160PIN|PLASTIC
TNETA1611PCA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Transceiver
TNETA1622 制造商:TI 制造商全稱:Texas Instruments 功能描述:622.08-MHz CLOCK-RECOVERY DEVICE
TNETA1622DW 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock/Data Recovery
TNETA1630DW 制造商:Texas Instruments 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*