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參數(shù)資料
| 型號： | TNETA1600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| 中文描述： | SONET / SDH的自動柜員機接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動柜員機接收器/傳送器） |
| 文件頁數(shù)： | 5/54頁 |
| 文件大小： | 1120K |
| 代理商： | TNETA1600 |
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TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
control signals
TERMINAL
NAME
I/O
DESCRIPTION
NO.
EN155
I
155.52-Mbit/s enable. When EN155 is high, data operations at 155.52 Mbit/s are enabled for both the
receiver and transmitter. In 155.52-Mbit/s mode, both the transmit- and receive-cell interfaces are byte wide
such that data are transmitted and received on TD0–TD7 and RD0–RD7, respectively. TD8–TD15 and
RD8–RD15 are not used. When EN155 is low, operations at 622.08 Mbit/s are enabled and all 16 bits of
the transmit-cell and receive-cell interfaces are utilized. Changing the mode between 155.52 Mbit/s and
622.08 Mbit/s during normal operation may result in the loss of data.
OE
I
Output enable. When OE is low, all outputs on the TNETA1600 go into the high-impedance state. This
feature facilitates board-level testing.
RESET
I
Device reset. When RESET goes low, the device is reset. This reset causes the receive side to restart the
frame search and forces OOF, LOF, and LOCA high. The reset also flushes any ATM cells stored in the input
and output FIFOs and causes the transmit side to begin building SONET frames from the A1 byte. A valid
clock must be present on TPCK when RESET transitions from low to high because this transition starts the
initialization of the transmit-overhead RAM.
SDHEN
I
SDH enable. When SDHEN is high, frames are transmitted with SDH overhead. SDHEN is logically ORed
with a bit in the control register such that both the bit and SDHEN must be low to transmit frames with SONET
overhead. A change in the logically ORed combination of SDHEN and the associated control bit causes the
transmit-RAM overhead to be overwritten with new SONET or SDH values, depending on the logically ORed
combination of SDHEN and the control bit as previously described. Because the overhead is altered, this
could result in the loss of data being processed in the transmitter.
TLB
I
Terminal loopback. TLB is logically ORed with a bit in the control register. If either or both are high, the data
received at the transmit-cell interface flows normally through the transmit path to the scrambling function,
where it is passed to the receive-framing function. The data is then processed through the receive path and
output on RD0–RD15. Data being received on RPD0–RPD7 is blocked. However, transmit operation is not
affected and output data is available on TPD0–TPD7.
receive-cell interface
TERMINAL
I/O
DESCRIPTION
NAME
NO.
RCKI
I
Receive clock input. Output data is valid on the receive-cell interface on positive transitions of RCKI when
RRE is low.
RD0–RD15
O
Receive output data. When EN155 is low (622.08-Mbit/s operation), ATM cell data is clocked out of the
TNETA1600 through RD0–RD15 on positive transitions of RCKI, beginning with the first two bytes of the
ATM header. When EN155 is high (155.52-Mbit/s operation), cells are clocked out on RD0–RD7
(RD8–RD15 are not used). RD0 is the least-significant bit.
RRE
I
Receive read enable. A low level on RRE enables the reading of data from the receive-cell interface.
RXSOC
O
Receive start of ATM-cell indicator. RXSOC goes high identifying the first byte (or first two bytes in
622.08-Mbit/s operation) of an ATM cell on the receive-cell interface. RXSOC is low during the remainder
of that cell’s output.
RXCLAV
O
Receive-cell available. RXCLAV goes high denoting that the receive output FIFO is capable of transferring
a complete ATM cell. RXCLAV goes low when the receive output FIFO is empty and the current output data
on RD0–RD15 is invalid.
P
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