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參數(shù)資料
| 型號： | TNETA1600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| 中文描述： | SONET / SDH的自動柜員機接收器/發(fā)送器為622.08，麻省理工學院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動柜員機接收器/傳送器） |
| 文件頁數(shù)： | 33/54頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | TNETA1600 |
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TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
33
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
B1-/B2-/B3-coding-violation counters
These counters keep a total of the number of receive B1, B2, and B3 bit-interleaved parity (BIP) bits that are
erred. When one of the counters reaches its maximum count, the INTR output goes active and a bit in the status
register is set. The counters automatically roll over to zero when they reach their maximum count.
B1-/B2-/B3-block-error counters
These counters keep a total of the number of frames received with B1, B2, and B3 errors. These counters track
the number of frames with errors, but not the number of actual B1, B2, and B3 bits in error. When they reach
their maximum count, the INTR output goes active and a bit in the status register is set. The counters
automatically roll over to zero when they reach their maximum count.
line-FEBE counter
This counter maintains a cumulative count of the number of incoming line FEBE reported through the receive
third Z2 byte. When the counter reaches its maximum count, the INTR output goes active and bit in the status
register is set. The counter automatically rolls over to zero when it reaches its maximum count.
path-FEBE counter
This counter maintains a cumulative count of the number of incoming path FEBE reported through the receive
G1 byte (bits 1-4). When the counter reaches its maximum count, the INTR output goes active and a bit in the
status register is set. The counter automatically rolls over to zero when it reaches its maximum count.
output ATM-cell counter
This counter provides a count of the number of cells placed in the receive output FIFO for subsequent output
on the receive cell interface. Cells dropped in the receive path (i.e., idle cells if bit 5 at address 007 hex is a zero)
are not included in this count. When the counter reaches its maximum count, the INTR output goes active and
a bit in the status register is set. The counter automatically rolls over to zero when it reaches it maximum count.
discarded-idle unassigned-cell counter
This counter provides a count of the number of idle, unassigned, or both idle and unassigned cells dropped,
dependent upon the configuration of the device as given in the control register. When the counter reaches its
maximum count, the INTR output goes active and a bit in the status register is set. The counter automatically
rolls over to zero when it reaches its maximum count.
single-bit-error ATM-cell counter
This counter provides a count of the number of ATM cells received with single-bit header errors. When the
counter reaches its maximum count, the INTR output goes active and a bit in the status register is set. The
counter automatically rolls over to zero when it reaches its maximum count.
multiple-bit-error ATM-cell counter
This counter provides a count of the number of received ATM cells with multiple-bit header errors. When the
counter reaches its maximum count, the INTR output goes active and a bit in the status register is set. The
counter automatically rolls over to zero when it reaches its maximum count.
receive-overhead RAM
The TNETA1600 stores the receive-overhead bytes in the receive-overhead RAM beginning at address 200.
There are 324 bytes in the transport overhead of a STS-12c signal and 36 bytes in the path overhead, for a total
of 360 overhead bytes in a STS-12c signal. In addition, the data-communications bytes (D1–12) and orderwire
bytes (E1 and E2) are also available through the serial receive data-communications port. Table 9 shows the
overhead bytes and their addresses in the receive-overhead RAM. If EN155 is high, only every fourth address
of the transport and path overhead is used (i.e., the three A1s are written to addresses 200, 204, and 208).
P
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PDF描述 |
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| TNETA1610 | STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器) |
| TNETA1611 | STS-12c/STM-4 Receiver/Transimitter(STS-12C/STM-4接收/傳送器) |
| TNETA1630 | 622.08-MHz Clock-Recovery Device(622.08-MHz時鐘發(fā)生裝置) |
| TO-252 | TO-252 (MP-3Z) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TNETA1600PCM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET FRAMER|QFP|160PIN|PLASTIC |
| TNETA1611PCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Transceiver |
| TNETA1622 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:622.08-MHz CLOCK-RECOVERY DEVICE |
| TNETA1622DW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock/Data Recovery |
| TNETA1630DW | 制造商:Texas Instruments 功能描述: |
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