參數(shù)資料
型號(hào)： TNETA1600
廠商： Texas Instruments, Inc.
英文描述： SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器)
中文描述： SONET / SDH的自動(dòng)柜員機(jī)接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動(dòng)柜員機(jī)接收器/傳送器）
文件頁(yè)數(shù)： 13/54頁(yè)
文件大小： 1120K
代理商： TNETA1600
TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
transmit overhead (continued)
In addition, the TNETA1600 can be programmed to transmit a LAIS or a PAIS by writing to specified bits in the
control registers. A LAIS is generated by the TNETA1600 as a valid SOH and a scrambled all-ones pattern for
the remainder of the signal. During a PAIS condition, the synchronous payload envelope (SPE) as well as the
H1, H2, and H3 pointer bytes are set to all ones before scrambling. When either the LAIS or PAIS condition is
transmitted, ATM cells loaded into the transmit-input FIFO are not inserted into the outgoing frame. This causes
the input FIFO to fill up once three ATM cells are input and the device does not accept additional ATM cells until
the device returns to normal operating mode. At that point, the device begins inserting ATM cells into the
outgoing frame. During a PAIS condition, all transport-overhead bytes (except H1, H2, and H3) in the outgoing
frame are calculated and inserted normally. Since the pointer bytes are set to all ones, the receiving station is
not able to locate the SPE and path-overhead bytes.
The TNETA1600 provides a serial-transmit data-communications port that allows data-communications and
orderwire bytes to be inserted into the outgoing transport overhead. The transmit data-communications
interface consists of a data-communication enable (TDEN) input, a serial data input (TSDI), a serial clock output
(TCO), and a framing pulse output (TFPO). TCO is a continuous clock signal that clocks out the framing pulse
and clocks in the serial data. The framing pulse is valid on the rising edge of TCO and is used to identify the
subsequent input of the most significant bit of the E1 byte. If TDEN is low when the MSB of a byte is to be input,
that byte is not read into the data-communications interface. If TDEN is high when the MSB of a given byte is
to be input, all eight bits of that byte are read into the transmit data-communications interface (on TSDI) on
contiguous clock cycles, MSB first. Bytes are read into the interface in the following order: E1, D1, D2, D3, D4,
D5, D6, D7, D8, D9, D10, D11, D12, E2. Provided TDEN is high, the MSB of the E1 byte is clocked into the device
on the first rising edge of TCO, immediately following the rising-clock edge that clocks out the framing pulse.
TCO has a frequency of 1.215 MHz. However, traffic is present on the data-communications interface only about
75% of the time as there are only 14 bytes (plus the framing pulse) to process each frame (125
μ
s), and all
14 bytes are read contiguously once TFPO is clocked out high. Orderwire- and data-communications bytes that
are input through the data-communications interface are written into the TNETA1600 internal RAM. The values
are then used in the overhead of subsequent frames, provided they are not overwritten through the controller
interface or by subsequent input through the data-communications port.
The TNETA1600 provides an 8-kHz reference output (TXREF8K) that is derived from the transmit-side
incoming clock signal. TXREF8K is a pulse that goes high during the period when the SONET scrambler is
disabled for the A1, A2, and C1 bytes. TXREF8K is low for the remainder of the frame. The pulse duration for
this signal is approximately 450 ns.
Prior to transmission, the output frame is scrambled using a generating polynomial of x
7
+ x
6
+ 1. The A1, A2,
and C1 overhead bytes are not scrambled and the scrambler is reset to 11111111 on the MSB of the byte
immediately following the last C1 byte. The scrambler runs continuously throughout the remainder of the frame.
The byte-wide data is output from the TNETA1600 upon detection of the rising edge of TPCK. The data is
accompanied by a return clock (RTNCK) such that the data is valid on the rising edge of RTNCK. This interface
runs at 19.44 MHz for 155.52-Mbit/s operation and 77.76 MHz for 622.08-Mbits/s operation. TPCK provides the
clock signal for the entire transmit-side operation, except for the transmit-cell-interface clock, which uses TCKI.
A terminal-loopback (TLB) feature is also provided on the TNETA1600. When the TLB bit in the control register
is set (or when TLB goes high), the ATM cells received on the transmit input flow normally through the transmit
path to the scrambling function where they are passed to the framing function in the receiver. The cells are then
processed through the receive path and output on RD0–RD15. Data received on RPD0–RPD7 is blocked.
However, the transmit operation is not affected in this mode and data is output on TPD0–TPD7 as well as being
passed to the receive path.
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