參數(shù)資料
型號(hào)： TNETA1600
廠商： Texas Instruments, Inc.
英文描述： SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器)
中文描述： SONET / SDH的自動(dòng)柜員機(jī)接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動(dòng)柜員機(jī)接收器/傳送器）
文件頁(yè)數(shù)： 38/54頁(yè)
文件大小： 1120K
代理商： TNETA1600
TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
38
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TAP controller
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This ensures that data (to be captured) is valid for fully one-half
of the TCK clock cycle. The TAP controller extracts the TCK and TMS signals from the interface and generates
the appropriate on-chip control signals for the test structures in the device. The TAP-controller state machine
is clocked on the rising edge of TCK. Figure 5 illustrates the state transitions of the TAP controller.
Test-Logic-Reset
TRST
Run-Test/Idle
TMS = H
TMS = L
Select-DR-Scan
Select-IR-Scan
TMS = H
TMS = H
TMS = H
TMS = L
Capture-DR
Capture-IR
Shift-DR
Shift-IR
Exit1-DR
Exit1-IR
Pause-DR
Pause-IR
Exit2-DR
Exit2-IR
Update-DR
Update-IR
TMS = L
TMS = H
TMS = L
TMS = L
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = L
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = L
TMS = L
TMS = L
TMS = L
TMS = H
Figure 4. TAP-Controller State Diagram
The definitions of the states associated with the TAP controller follow:
test-logic-reset
TRST should be held low during device power-up to cause the TAP controller to enter the Test-Logic-Reset
state. In the stable Test-Logic-Reset state, the test logic is reset and disabled so that the normal function of the
device is performed. This state is entered asynchronously by asserting TRST. This state is entered
synchronously in no more than five TCK cycles if TMS is left high. While in this state, the instruction register
is set to the IDCODE instruction. Each bit in the boundary-scan register is reset to logic zero, except bits TBD,
which are reset to logic one.
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