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參數(shù)資料
| 型號： | TLIU04C1 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface(四T1/E1線接口) |
| 中文描述： | 四T1/E1線路接口（四個(gè)T1/E1線接口） |
| 文件頁數(shù)： | 89/100頁 |
| 文件大小： | 1321K |
| 代理商： | TLIU04C1 |
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Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
89
Lucent Technologies Inc.
Direct Logic Control Mode
(continued)
Loopbacks
The device has three independent loopback paths that
are activated using the FLLOOP RLOOP and DLLOOP
pins. The locations of these loopbacks are illustrated in
Figure 26.
Full Local Loopback (FLLOOP)
A full local loopback (FLLOOP) connects the transmit
line driver input to the receiver analog front-end cir-
cuitry. Valid transmit output data continues to be sent to
the network. If the transmit AIS (all-ones signal) is sent
to the network, the looped data is not affected. The
ALOS alarm continues to monitor the receive line inter-
face signal while DLOS monitors the looped data.
Remote Loopback (RLOOP)
A remote loopback (RLOOP) connects the recovered
clock and retimed data to the transmitter at the system
interface and sends the data back to the line. The
receiver front end, clock/data recovery, encoder/
decoder (if enabled) jitter attenuator (if enabled), and
transmit driver circuitry are all exercised during this
loopback. The transmit clock, transmit data, and XAIS
inputs are ignored. Valid receive output data continues
to be sent to the system interface. This loopback mode
is very useful for isolating failures between systems.
Digital Local Loopback (DLLOOP)
A digital local loopback (DLLOOP) connects the trans-
mit clock and data through the encoder/decoder pair to
the receive clock and data output pins at the system
interface. This loopback is operational if the encoder/
decoder pair is enabled or disabled. The AIS signal can
be transmitted without any effect on the looped signal.
Powerdown (PWRDN)
Each line interface channel has an independent power-
down mode controlled by PWRDN. This provides
power savings for systems that use backup channels. If
PWRDN = 1, the corresponding channel will be in a
standby mode, consuming only a small amount of
power. If a line interface channel in powerdown mode
needs to be placed into service, the channel should be
turned on (PWRDN = 0) approximately 5 ms before
data is applied.
Reset (RESET)
The device provides a hardware reset (
RESET
; pin 44).
When the device is in reset, all signal-path and alarm
monitor states are initialized to a known starting config-
uration. During a reset condition, data transmission will
be interrupted.
The reset condition is initiated by setting
RESET
= 0 for
a minimum of 10 μs. On coming out of the reset condi-
tion (RESET = 1), a time of at least 2.7 ms should be
allowed to ensure stabilization of the PLL.
Loss of XCLK Reference Clock (LOXC)
The LOXC output (pin 45) is active when the XCLK ref-
erence clock (pin 46) is absent. The LOXC flag is
asserted a maximum of 16 μs after XCLK disappears,
and deasserts immediately after detecting the first
clock edge of XCLK.
During the LOXC alarm condition, the clock recovery
and jitter attenuator functions are automatically dis-
abled. Therefore, if CDR = 1 and/or JAR = 1, the RCLK,
RPD, RND, and DLOS outputs will be unknown. If CDR
= 0, there will be no effect on the receiver. If the jitter
attenuator is enabled in the transmit path (JAT = 1) dur-
ing this alarm condition, then a loss of transmit clock
alarm, LOTC = 1, will also be indicated.
In-Circuit Testing and Driver High-Imped-
ance State (ICT)
The affect of asserting the
ICT
input (pin 43) is that all
output buffers (TTIP TRING, RCLK, RPD, RND, LOXC,
RDY_
DTACK
, INT, AD[7:0]) are placed in a high-imped-
ance state. The TTIP and TRING outputs have a limit-
ing high-impedance capability of approximately 8 k
.
LIU Delay Values
The transmit coder has 5 UI delay whether it is in the
path or not and whether it is B8ZS or HDB3. Its delay is
only removed when in single-rail mode. The remainder
of the transmit path has 4.6 UI delay. The receive
decoder has 5 UI delay whether it is in the path or not
and whether it is B8ZS or HDB3. Its delay is only
removed when in single-rail mode or CDR = 0. The
AFE (equalizer plus slicer) delay is nearly 0 UI delay.
The jitter attenuator delay is nominally 33 UI but can be
2 UI—64 UI depending on the state. The DPLL used for
timing recovery has 8 UI delay.
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