參數(shù)資料
型號(hào)： TLIU04C1
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface(四T1/E1線接口)
中文描述： 四T1/E1線路接口（四個(gè)T1/E1線接口）
文件頁(yè)數(shù)： 4/100頁(yè)
文件大?。?/td> 1321K
代理商： TLIU04C1
Advance Data Sheet, Rev. 2
TLIU04C1 Quad T1/E1 Line Interface
April 1999
4
Lucent Technologies Inc.
Table of Contents
(continued)
Contents
Page
DS1 Transmitter Pulse Template....................................................................................................................... 80
CEPT Transmitter Pulse Template..................................................................................................................... 81
Jitter Attenuator.................................................................................................................................................. 82
Generated (Intrinsic) Jitter .............................................................................................................................. 82
Jitter Transfer Function................................................................................................................................... 83
Jitter Accommodation ..................................................................................................................................... 83
Jitter Attenuator Enable .................................................................................................................................. 84
Jitter Attenuator Receive Path Enable (JAR).................................................................................................. 84
Jitter Attenuator Transmit Path Enable (JAT) ................................................................................................. 84
Frequency Response Curves ......................................................................................................................... 85
Loopbacks.......................................................................................................................................................... 89
Full Local Loopback (FLLOOP) ...................................................................................................................... 89
Remote Loopback (RLOOP)........................................................................................................................... 89
Digital Local Loopback (DLLOOP).................................................................................................................. 89
Powerdown (PWRDN)........................................................................................................................................ 89
Reset (
RESET
).................................................................................................................................................... 89
Loss of XCLK Reference Clock (LOXC)............................................................................................................. 89
In-Circuit Testing and Driver High-Impedance State (ICT)................................................................................. 89
LIU Delay Values................................................................................................................................................ 89
Line Encoding/Decoding .................................................................................................................................... 90
Alternate Mark Inversion (AMI) ....................................................................................................................... 90
T1-Binary 8 Zero Code Suppression .............................................................................................................. 90
High-Density Bipolar of Order 3 (HDB3)......................................................................................................... 90
XCLK Reference Clock ...................................................................................................................................... 91
16x XCLK Reference Clock ............................................................................................................................ 91
Primary Line Rate XCLK Reference Clock and Internal Reference Clock Synthesizer.................................. 92
Power Supply Bypassing.................................................................................................................................... 93
Line Circuitry ...................................................................................................................................................... 94
Absolute Maximum Ratings................................................................................................................................ 95
Handling Precautions......................................................................................................................................... 95
Operating Conditions.......................................................................................................................................... 95
Power Requirements.......................................................................................................................................... 96
Electrical Characteristics.................................................................................................................................... 96
Data Interface Timing......................................................................................................................................... 97
Outline Diagram..................................................................................................................................................... 98
144-Pin TQFP ..................................................................................................................................................... 98
Ordering Information.............................................................................................................................................. 99
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