參數(shù)資料
            型號(hào): TLIU04C1
            廠商: Lineage Power
            英文描述: Quad T1/E1 Line Interface(四T1/E1線接口)
            中文描述: 四T1/E1線路接口(四個(gè)T1/E1線接口)
            文件頁(yè)數(shù): 52/100頁(yè)
            文件大小: 1321K
            代理商: TLIU04C1
            Advance Data Sheet, Rev. 2
            TLIU04C1 Quad T1/E1 Line Interface
            April 1999
            52
            Lucent Technologies Inc.
            Microprocessor Mode
            (continued)
            Power Requirements
            The majority of the power used by the TLIU04C1 device is used by the line drivers. Therefore, the power is very
            dependent on data pattern and signal amplitude. The signal amplitude is a function of the transmit equalization in
            DS1 mode. When configured for greater cable loss, the signal amplitude is greater at the output drivers, and thus
            uses more power. For this reason, the power specification of Table 34 are given for various conditions. The typical
            specification is for a quasi-random signal and the maximum specification is for a mark (all ones) pattern. The power
            also varies somewhat for DS1 versus CEPT, so figures are given for both.
            Table 34. Power Consumption
            Power dissipation is the amount of power dissipated in the device. It is equal to the power drawn by the device
            minus the power dissipated in the line.
            Table 35. Power Dissipation
            Electrical Characteristics
            Parameter
            Power
            Unit
            Typ
            TBD
            TBD
            TBD
            Max
            TBD
            TBD
            TBD
            CEPT
            DS1
            DS1 with Max Eq.
            mW
            mW
            mW
            Parameter
            Power
            Unit
            Typ
            TBD
            TBD
            TBD
            Max
            TBD
            TBD
            TBD
            CEPT
            DS1
            DS1 with Max Eq.
            mW
            mW
            mW
            Table 36. Logic Interface Characteristics
            Note:
            The following internal resistors are provided: 50 k
            pull-up on the
            ICT
            and
            RESET
            pins, 50 k
            pull-down on
            the CLKS and CLKM pins, and 100 k
            pull-up on the
            CS
            , and XCLK pins. This requires these input pins to
            sink no more than 20 μA. The device uses TTL input and output buffers; all buffers are CMOS-compatible.
            Parameter
            Symbol
            Test Conditions
            Min
            Max
            Unit
            Input Voltage:
            Low
            High
            Input Leakage
            Output Voltage:
            Low
            High
            Input Capacitance
            Load Capacitance
            *
            V
            IL
            V
            IH
            I
            L
            GND
            D
            2.1
            0.8
            V
            DDD
            10
            V
            V
            μA
            V
            OL
            V
            OH
            C
            I
            C
            L
            I
            OL
            = –5.0 mA
            I
            OH
            = 5.0 mA
            GND
            D
            V
            DDD
            – 0.5
            0.4
            V
            DDD
            3.0
            50
            V
            V
            pF
            pF
            * 100 pF allowed for AD[7:0] (pins 75—82).
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