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參數(shù)資料
| 型號(hào)： | TLIU04C1 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface(四T1/E1線接口) |
| 中文描述： | 四T1/E1線路接口（四個(gè)T1/E1線接口） |
| 文件頁(yè)數(shù)： | 13/100頁(yè) |
| 文件大?。?/td> | 1321K |
| 代理商： | TLIU04C1 |
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Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
13
Lucent Technologies Inc.
Microprocessor Mode
(continued)
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
Pin
Symbol
Type
*
* I = input, O = output, I
u
indicates an input with internal pull-up; I
d
indicates an input with internal pull-down, P = power. Resistance value of all
internal pull-ups or pull-downs is 50 k
, unless otherwise specified.
Name/Description
43
ICT
I
u
In-Circuit Test Control (Active-Low)
.
If
ICT
is forced low, certain output pins
are placed in a high-impedance state. Which output pins are affected is
controlled by the ICTMODE bit (register 4, bit 3).
75—82
AD[7:0]
I/O
Microprocessor Interface Address/Data Bus.
If MPMUX = 0 (pin 108),
these pins become the bidirectional, 3-statable data bus. If MPMUX = 1,
these pins become the multiplexed address/data bus. In this mode, only the
lower 4 bits (AD[3:0]) are used for the internal register addresses.
7—10
A[3:0]
I
Microprocessor Interface Address.
If MPMUX = 0 (pin 108), these pins
become the address bus for the microprocessor interface registers. If
MPMUX = 1 (pin 108) and CS = 0 (pin 113), A3 (pin 7) can be externally tied
high to use the internal chip selection function. The state of A[2:0] determines
the address of the device. The device is addressed when the state of pins
AD[6:4] matches the device address of A[2:0]. If this function is not used,
A[3:0] must be externally tied low.
106
MPCLK
I
Microprocessor Interface Clock.
Microprocessor interface clock rates from
twice the frequency of the line clock (3.088 MHz for DS1 operation,
4.096 MHz for CEPT operation) to 16.384 MHz are supported.
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