參數(shù)資料
型號： TLIU04C1
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface(四T1/E1線接口)
中文描述： 四T1/E1線路接口（四個T1/E1線接口）
文件頁數(shù)： 48/100頁
文件大?。?/td> 1321K
代理商： TLIU04C1
Advance Data Sheet, Rev. 2
TLIU04C1 Quad T1/E1 Line Interface
April 1999
48
Lucent Technologies Inc.
Microprocessor Mode
(continued)
XCLK Reference Clock
The device requires an externally applied clock, XCLK (pin 46), for the clock and data recovery function and the jit-
ter attenuation option. XCLK must be a continuously active (i.e., ungapped, unjittered, and unswitched) and an
independent reference clock such as from an external system oscillator or system clock for proper operation. It
must not be derived from any recovered line clock (i.e., from RCLK or any synthesized frequency of RCLK).
XCLK may be supplied in one of four formats; 16x DS1, DS1, 16x CEPT, or CEPT. The format is selected globally
for the device by CLKS (pin 117) and CLKM (pin 116).
CLKS determines the relationship between the primary line data rate and the clock signal applied to XCLK. For
CLKS = 0, a clock at 16x the primary line data rate clock (24.704 MHz for DS1 and 32.768 MHz for CEPT) must be
applied to XCLK. For CLKS = 1, a primary line data rate clock (1.544 MHz for DS1 and 2.048 MHz for CEPT) must
be applied to XCLK.
The CLKS pin has an internal pull-down resistor allowing the pin to be left open, i.e., a no connect, in applications
using a 16x reference clock. The CLKS pin must be pulled up to V
DD
for applications using a primary line data rate
clock.
CLKM determines whether the clock synthesizer is operating in CEPT or DS1 mode when XCLK is a primary line
data rate clock. For CLKM = 0, the clock synthesizer operates in DS1 mode (1.544 MHz). For CLKM = 1, the clock
synthesizer operates in CEPT mode (2.048 MHz). The CLKM pin is ignored when CLKS = 0.
The CLKM pin has an internal pull-down resistor allowing the pin to be left open, i.e., a no connect, in applications
using a DS1 line rate reference clock. The CLKM pin must be pulled up to V
DD
for applications using a CEPT line
data rate clock.
16x XCLK Reference Clock
The specifications for XCLK using a 16x reference clock are defined in Table 28. The 16x reference clock is
selected when CLKS = 0.
Table 28. XCLK (16x, CLKS = 0) Timing Specifications
* When JABW0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on XCLK should be tightened to ±20 ppm in order to
meet the jitter accommodation requirements of TBR12/13 as given in G.823 for line data rates of ±50 ppm.
If XCLK is used as the source for AIS (see Alarm Indication Signal Generator (XAIS) on page 30), it must meet the nominal transmission
specifications of 1.544 MHz ± 32 ppm for DS1 (T1) or 2.048 MHz ± 50 ppm for CEPT (E1).
Parameter
Value
Unit
Min
Typ
Max
Frequency:
DS1
CEPT
Range*,
Duty Cycle
—
—
24.704
32.768
—
—
—
—
100
60
MHz
MHz
ppm
%
–100
40
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