參數(shù)資料
型號(hào): TLIU04C1
廠商: Lineage Power
英文描述: Quad T1/E1 Line Interface(四T1/E1線接口)
中文描述: 四T1/E1線路接口(四個(gè)T1/E1線接口)
文件頁(yè)數(shù): 80/100頁(yè)
文件大?。?/td> 1321K
代理商: TLIU04C1
Advance Data Sheet, Rev. 2
TLIU04C1 Quad T1/E1 Line Interface
April 1999
80
Lucent Technologies Inc.
Direct Logic Control Mode
(continued)
DS1 Transmitter Pulse Template
The DS1 pulse shape template is specified at the DSX
(defined by CB119 and ANSI T1.102) and is illustrated
in Figure 31. The device also meets the pulse template
specified by ITU-T G.703 (not shown).
5-1160(F)r.1
Figure 31. DSX-1 Isolated Pulse Template
Table 46. DSX-1 Pulse Template Corner Points
(from CB119)
1.0
0.5
0
–0.5
0
250
500
750
1000
1250
TIME (ns)
Maximum Curve
Minimum Curve
ns
V
ns
V
0
250
325
325
425
500
675
725
1100
1250
0.05
0.05
0.80
1.15
1.15
1.05
1.05
–0.07
0.05
0.05
0
350
350
400
500
600
650
650
800
925
1100
1250
–0.05
–0.05
0.50
0.95
0.95
0.90
0.50
–0.45
–0.45
–0.20
–0.05
–0.05
During DS1 operation, the TTIP and TRING pins will perform as specified in Table 47.
1. In accordance with the line circuitry described (see Line Circuitry on page 94).
2.Total power difference.
3.Measured in a 2 kHz band around the specified frequency.
4.Using Lucent transformer 2795B and components in Table 55.
5.Below the power at 772 kHz.
Table 47. DS1 Transmitter Specifications
Parameter
Min
Typ
Max
Unit
Spec
Output Pulse Amplitude at DSX
1
Output Pulse Width at Line Side of
Transformer
1
Output Pulse Width at Device Pins
TTIP and TRING
1
Positive/Negative Pulse Imbalance
2
Power Levels
3, 4
:
772 kHz
1.544 MHz
5
2.5
325
3.0
350
3.5
375
V
ns
AT&T CB119,
ANSI T1.102
330
350
370
ns
0.1
0.4
dB
12.6
29
39
17.9
dBm
dB
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