- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371186 > TLIU04C1 (Lineage Power) Quad T1/E1 Line Interface(四T1/E1線接口) PDF資料下載
參數(shù)資料
| 型號： | TLIU04C1 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface(四T1/E1線接口) |
| 中文描述： | 四T1/E1線路接口（四個T1/E1線接口） |
| 文件頁數(shù)： | 16/100頁 |
| 文件大?。?/td> | 1321K |
| 代理商： | TLIU04C1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁
Advance Data Sheet, Rev. 2
TLIU04C1 Quad T1/E1 Line Interface
April 1999
16
Lucent Technologies Inc.
Microprocessor Mode
(continued)
Microprocessor Clock (MPCLK) Specifications
The microprocessor interface is designed to operate at clock speeds up to 16.384 MHz without requiring any wait-
states. Wait-states may be needed if higher microprocessor clock speeds are required. The microprocessor clock
(MPCLK, pin 106) specification is shown in Table 5. This clock must be supplied only if the RDY_DTACK and INT
outputs are required to be synchronous to MPCLK. Otherwise, the MPCLK pin must be connected to ground.
Internal Chip Select Function
When the microprocessor interface is configured to operate in the multiplexed address/data bus modes
(MPMUX = 1), the user has access to an internal chip select function. This function allows a microprocessor to
selectively read or write a specific TLIU04C1 device in a system of up to eight devices on the microprocessor bus.
Externally tying CS = 0 (pin 113) and A3 = 1 (pin 7) on every device enables the internal chip select function. Indi-
vidual device addresses are established by externally connecting the other three address pins, A[2:0] (pins 8, 9,
10), to a unique address value in the range of 000 through 111. In order for a device to respond to the register read
or write request from the microprocessor, the address data bus AD[6:4] (pins 76, 77, 78) must match the specific
address defined on A[2:0]. If
CS
and A3 pins are tied low, the internal chip select function is disabled and all
devices will respond to a microprocessor write request. However, if
CS
= 1, none of the devices will respond to the
microprocessor read/write request.
The I/O timing specifications for the microprocessor interface are given on page 53.
Table 5. Microprocessor Input Clock Specifications
Name
Period and
Tolerance
T
rise
Typ
T
fall
Typ
Duty Cycle
Unit
Min High
Min Low
MPCLK
61 to 323
5
5
27
27
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLV3011AIDBVR | Nanopower, 1.8V, SOT23 Comparator with Voltage Reference |
| TLV349x | CAPACITOR, CLASS Y2 1.0NFCAPACITOR, CLASS Y2 1.0NF; Capacitance:1nF; Voltage rating, AC:250V; Voltage rating, DC:2500V; Capacitor dielectric type:Polypropylene; Series:B81122; Tolerance, +:20%; Tolerance, -:20%; Temp, op. |
| TLV3011AIDBVT | Nanopower, 1.8V, SOT23 Comparator with Voltage Reference |
| TLV3011AIDCKR | Nanopower, 1.8V, SOT23 Comparator with Voltage Reference |
| TLV3011AIDCKT | Nanopower, 1.8V, SOT23 Comparator with Voltage Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLIXF30001 | 制造商:GIGA 功能描述: |
| TLIXF30003 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TLIXF30007-852838 | 制造商:Cortina Systems Inc 功能描述: |
| TLIXF30009-865852 | 功能描述:IC OPT TRANSPORT PROC 868-TBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| TLIXF30010 | 制造商:Intel 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。