參數(shù)資料
型號(hào)： TLIU04C1
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface(四T1/E1線接口)
中文描述： 四T1/E1線路接口（四個(gè)T1/E1線接口）
文件頁(yè)數(shù)： 2/100頁(yè)
文件大?。?/td> 1321K
代理商： TLIU04C1
Advance Data Sheet, Rev. 2
TLIU04C1 Quad T1/E1 Line Interface
April 1999
2
Lucent Technologies Inc.
Table of Contents
Contents
Page
Features .................................................................................................................................................................. 1
Applications............................................................................................................................................................. 1
Description............................................................................................................................................................... 8
Microprocessor Mode.............................................................................................................................................. 8
Overview .............................................................................................................................................................. 8
Pin Information..................................................................................................................................................... 9
System Interface Pin Options............................................................................................................................. 14
Microprocessor Configuration Modes................................................................................................................. 14
Microprocessor Interface Pinout Definitions....................................................................................................... 15
Microprocessor Clock (MPCLK) Specifications.................................................................................................. 16
Internal Chip Select Function............................................................................................................................. 16
Microprocessor Interface Register Architecture................................................................................................. 17
Block Diagrams.................................................................................................................................................. 18
Data Recovery.................................................................................................................................................... 20
Jitter Accommodation and Jitter Transfer Without the Jitter Attenuator............................................................. 20
Receiver Configuration Modes........................................................................................................................... 20
Clock/Data Recovery Mode (CDR)................................................................................................................. 20
Zero Substitution Decoding (CODE)............................................................................................................... 20
Alternate Logic Mode (ALM) ........................................................................................................................... 21
Alternate Clock Mode (ACM) .......................................................................................................................... 21
RLIU Alarms.................................................................................................................................................... 21
DS1 Receiver Specifications.............................................................................................................................. 23
Frequency Response Curves ......................................................................................................................... 24
CEPT Receiver Specifications ........................................................................................................................... 26
Frequency Response Curves ......................................................................................................................... 27
Output Pulse Generation.................................................................................................................................... 29
Jitter.................................................................................................................................................................... 29
Zero Substitution Encoding (CODE) .................................................................................................................. 30
Alarm Indication Signal Generator (XAIS) ...................................................................................................... 30
Transmitter Alarms............................................................................................................................................. 30
Loss of Transmit Clock (LOTC) Alarm............................................................................................................ 30
Transmit Driver Monitor (TDM) Alarm............................................................................................................. 30
DS1 Transmitter Pulse Template and Specifications......................................................................................... 31
CEPT Transmitter Pulse Template and Specifications ...................................................................................... 33
Jitter Attenuator.................................................................................................................................................. 34
Generated (Intrinsic) Jitter .............................................................................................................................. 34
Jitter Transfer Function................................................................................................................................... 35
Jitter Accommodation ..................................................................................................................................... 35
Jitter Attenuator Enable .................................................................................................................................. 36
Jitter Attenuator Receive Path Enable (JAR).................................................................................................. 36
Jitter Attenuator Transmit Path Enable (JAT) ................................................................................................. 36
Frequency Response Curves ......................................................................................................................... 37
Loopbacks.......................................................................................................................................................... 41
Full Local Loopback (FLLOOP) ...................................................................................................................... 41
Remote Loopback (RLOOP)........................................................................................................................... 41
Digital Local Loopback (DLLOOP).................................................................................................................. 41
Powerdown (PWRDN)........................................................................................................................................ 42
Reset (
RESET
, SWRESET)................................................................................................................................ 42
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