
Advance Data Sheet, Rev. 2
TLIU04C1 Quad T1/E1 Line Interface
April 1999
10
Lucent Technologies Inc.
Microprocessor Mode
(continued)
Pin Information
(continued)
Table 1. Pin Descriptions
* I = input, O = output, I
u
indicates an input with internal pull-up; I
d
indicates an input with internal pull-down, P = power. Resistance value of all
internal pull-ups or pull-downs is 50 k
, unless otherwise specified.
Pin
Symbol
Type
*
I
d
Name/Description
117
CLKS
XCLK Select.
This pin selects either a 16x rate clock for XCLK (CLKS = 0)
or a primary line rate clock for XCLK (CLKS = 1).
XCLK Mode.
This pin must be set appropriately when using a primary line
rate clock for XCLK.
CEPT:
CLKM = 1.
DS1:
CLKM = 0.
Chip Mode.
This pin sets the chip mode for either direct logic mode or
microprocessor mode.
116
CLKM
I
d
118
CMODE
I
d
Microprocessor: CMODE = 1.
Direct Logic: CMODE = 0.
Ground Reference for Line Drivers.
128, 132
25, 29,
56, 60,
97, 101
129, 28,
57, 100
130, 27,
58, 99
131, 26,
59, 98
133, 24,
61, 96
134, 23,
62, 95
135, 22,
63, 94
136, 21,
64, 93
137, 20,
65, 92
GND
X
[1—4]
P
TTIP[1—4]
O
Transmit Bipolar Tip.
Positive bipolar transmit data to the analog line
interface.
Power Supply for Line Drivers.
The TLIU04C1 device requires a 5 V ± 5%
power supply on these pins.
Transmit Bipolar Ring.
Negative bipolar transmit data to the analog line
interface.
Power Supply for Analog Circuitry.
The TLIU04C1 device requires a 5 V
± 5% power supply on these pins.
Receive Bipolar Tip.
Positive bipolar receive data from the analog line
interface.
Receive Bipolar Ring.
Negative bipolar receive data from the analog line
interface.
Ground Reference for Analog Circuitry.
V
DDX
[1—4]
P
TRING[1—4]
O
V
DDA
[1—4]
P
RTIP[1—4]
I
RRING[1—4]
I
GND
A
[1—4]
P
RND/BPV[1—4]
O
Receive Negative Data.
When in dual-rail (DUAL = 1: register 5, bit 4)
clock recovery mode (CDR = 1: register 5, bit 0), this signal is the received
negative NRZ data to the terminal equipment. When in data slicing mode
(CDR = 0), this signal is the raw sliced negative data of the front end.
Bipolar Violation.
When in single-rail (DUAL = 0: register 5, bit 4) clock
recovery mode (CDR = 1: register 5, bit 0), and CODE = 1 (register 5, bit 3),
this signal is asserted high to indicate the occurrence of a code violation in
the receive data stream. A code violation is a bipolar violation that is not
part of a zero substitution code. If CODE = 0, this signal is asserted to
indicate the occurrence of a bipolar violation in the received data.