參數(shù)資料
型號(hào)： TLIU04C1
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface(四T1/E1線接口)
中文描述： 四T1/E1線路接口（四個(gè)T1/E1線接口）
文件頁(yè)數(shù)： 14/100頁(yè)
文件大?。?/td> 1321K
代理商： TLIU04C1
Advance Data Sheet, Rev. 2
TLIU04C1 Quad T1/E1 Line Interface
April 1999
14
Lucent Technologies Inc.
Microprocessor Mode
(continued)
System Interface Pin Options
The system interface can be configured to operate in a number of different modes. The different modes change the
functionality of the system interface pins, as shown in Table 2. Dual-rail or single-rail operation is possible using the
DUAL control bit (register 5, bit 4). Dual-rail mode is enabled when DUAL = 1; single-rail mode is enabled when
DUAL = 0. In dual-rail operation, data received from the line interface on RTIP and RRING appears on RPD and
RND at the system interface and data transmitted from the system interface on TPD and TND appears on TTIP and
TRING at the line interface. In single-rail operation, data received from the line interface on RTIP and RRING
appears on RDATA at the system interface and data transmitted from the system interface on TDATA appears on
TTIP and TRING at the line interface.
In both dual-rail and single-rail operation, the clock/data recovery mode is selectable via the CDR bit (register 5,
bit 0). When CDR = 1, the clock and data recovery is enabled and the system interface operates in a nonreturn-to-
zero (NRZ) digital format, recovering the clock and data from the incoming pulses. When CDR = 0, the clock and
data recovery is disabled and the system interface operates on unretimed sliced data in RZ data format. No clock is
recovered, freeing up the RCLK pin to be used to indicate an analog loss of signal (ALOS). If the incoming pulse
height falls below –18 dB, the ALOS pin is asserted high, and remains high until the signal rises above –14 dB.
In single-rail mode only, B8ZS/HDB3 encoding/decoding may be selected by setting the control bits properly (see
the Zero Substitution Decoding (CODE) section, page 20, and the Zero Substitution Encoding (CODE) section,
page 30). When a coding violations occurs, the BPV pin is asserted high.
Table 2. System Interface Pin Mapping
Microprocessor Configuration Modes
Table 3 highlights the four microprocessor modes controlled by the MPMUX and MPMODE inputs (pins 108 and
110).
Configuration
RCLK/
ALOS
RCLK
RPD/
RDATA
RPD
RND/BPV
TPD/
TDATA
TPD
TND
Dual-rail with Clock Recovery (DUAL = 1,
CDR = 1)
Dual-rail with Data Slicing (DUAL = 1, CDR = 0)
Single-rail with Clock Recovery (DUAL = 0,
CDR = 1)
Single-rail with Data Slicing (DUAL = 0, CDR = 0)
RND
TND
ALOS
RCLK
RPD
RDATA
RND
BPV
TDATA
Not Used
ALOS
RPD
RND
Table 3. Microprocessor Configuration Modes
Mode
MPMODE
MPMUX
Address/Data Bus
Generic Control, Data, and
Output Pin Names
CS
,
AS
,
DS
, R/
W
, A[3:0], AD[7:0], INT,
DTACK
CS
,
AS
,
DS
, R
/W
, AD[7:0], INT,
DTACK
CS
, ALE,
RD
,
WR
, A[3:0], AD[7:0], INT, RDY
CS
, ALE,
RD
,
WR
, AD[7:0], INT, RDY
MODE 1
MODE 2
MODE 3
MODE 4
0
0
1
1
0
1
0
1
deMUXed
MUXed
deMUXed
MUXed
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