參數(shù)資料
型號： TLIU04C1
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface(四T1/E1線接口)
中文描述： 四T1/E1線路接口（四個T1/E1線接口）
文件頁數(shù)： 3/100頁
文件大?。?/td> 1321K
代理商： TLIU04C1
Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
3
Lucent Technologies Inc.
Table of Contents
(continued)
Contents
Page
Loss of XCLK Reference Clock (LOXC)............................................................................................................. 42
In-Circuit Testing and Driver High-Impedance State (ICT)................................................................................. 42
LIU Delay Values................................................................................................................................................ 42
Line Encoding/Decoding .................................................................................................................................... 43
Alternate Mark Inversion (AMI) ....................................................................................................................... 43
T1-Binary 8 Zero Code Suppression (B8ZS).................................................................................................. 43
High-Density Bipolar of Order 3 (HDB3)......................................................................................................... 43
Registers............................................................................................................................................................ 44
Alarm Registers (0000, 0001)......................................................................................................................... 44
Alarm Mask Registers (0010, 0011)................................................................................................................ 45
Global Control Registers (0100, 0101)............................................................................................................ 45
Channel Configuration and Control Registers (0110—1001, 1011, 1100)...................................................... 46
XCLK Reference Clock ...................................................................................................................................... 48
16x XCLK Reference Clock ............................................................................................................................ 48
Primary Line Rate XCLK Reference Clock and Internal Reference Clock Synthesizer.................................. 49
Power Supply Bypassing.................................................................................................................................... 49
Line Circuitry ...................................................................................................................................................... 50
Absolute Maximum Ratings................................................................................................................................ 51
Handling Precautions......................................................................................................................................... 51
Operating Conditions.......................................................................................................................................... 51
Power Requirements.......................................................................................................................................... 52
Electrical Characteristics.................................................................................................................................... 52
Microprocessor Interface Timing........................................................................................................................ 53
Data Interface Timing......................................................................................................................................... 59
Direct Logic Control Mode..................................................................................................................................... 60
Overview ............................................................................................................................................................ 60
Device Overview ................................................................................................................................................ 60
Pin Information................................................................................................................................................... 61
System Interface Pin Options............................................................................................................................. 66
Block Diagrams.................................................................................................................................................. 67
Data Recovery.................................................................................................................................................... 69
Jitter Accommodation and Jitter Transfer Without the Jitter Attenuator............................................................. 69
Receiver Configuration Modes........................................................................................................................... 69
Clock/Data Recovery Mode (CDR)................................................................................................................. 69
Zero Substitution Decoding (CODE)............................................................................................................... 69
Alternate Logic Mode (ALM) ........................................................................................................................... 69
Alternate Clock Mode (ACM) .......................................................................................................................... 69
RLIU Alarms.................................................................................................................................................... 70
DS1 Receiver Specifications.............................................................................................................................. 72
Frequency Response Curves.......................................................................................................................... 73
CEPT Receiver Specifications ........................................................................................................................... 75
Frequency Response Curves.......................................................................................................................... 76
Output Pulse Generation.................................................................................................................................... 78
Jitter.................................................................................................................................................................... 78
Transmitter Configuration Modes....................................................................................................................... 79
Zero Substitution Encoding (CODE)............................................................................................................... 79
Alarm Indication Signal Generator (XAIS)....................................................................................................... 79
Loss of Transmit Clock (LOTC) Alarm............................................................................................................ 79
Transmit Driver Monitor (TDM) Alarm............................................................................................................. 79
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