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參數(shù)資料
| 型號(hào)： | TLIU04C1 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface(四T1/E1線接口) |
| 中文描述： | 四T1/E1線路接口（四個(gè)T1/E1線接口） |
| 文件頁(yè)數(shù)： | 17/100頁(yè) |
| 文件大小： | 1321K |
| 代理商： | TLIU04C1 |
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Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
17
Lucent Technologies Inc.
Microprocessor Mode
(continued)
Microprocessor Interface Register Architecture
The register bank architecture of TLIU04C1 consists of a register bank for the quad line interface unit. The register
bank consists of sixteen 8-bit registers comprising the alarm, control, and configuration registers for the quad line
interface unit.
Table 6 shows the register bank architecture.
Notes:
A numerical suffix appended to the bit name identifies the channel number.
Bits shown in parentheses indicate the state forced during a reset condition.
All registers must be configured by the user before the device can operate as required for the particular application.
Table 6. LIU Register Bank
Designation
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Alarm Registers (Read Only)
0
0000
LOTC2
TDM2
DLOS2
ALOS2
LOTC1
TDM1
DLOS1
ALOS1
1
0001
LOTC4
TDM4
DLOS4
ALOS4
LOTC3
TDM3
DLOS3
ALOS3
Alarm Mask Registers (Read/Write)
2
0010
MLOTC2
MTDM2
MDLOS2
MALOS2
MLOTC1
MTDM1
MDLOS1
MALOS1
3
0011
MLOTC4
MTDM4
MDLOS4
MALOS4
MLOTC3
MTDM3
MDLOS3
MALOS3
Global Control Registers (Read/Write)
4
0100
HIGHZ4 (1)
HIGHZ3 (1)
HIGHZ2 (1) HIGHZ1 (1) ICTMODE (0)
LOSSTD
SWRESET
(0)
GMASK (1)
5
0101
LOSSD
ACM
ALM
DUAL
CODE
JAT
JAR
CDR
Channel Configuration Registers (Read/Write)
6
0110
EQA1
EQB1
EQC1
LOOPA1
LOOPB1
XAIS1
MASK1
PWRDN1
7
0111
EQA2
EQB2
EQC2
LOOPA2
LOOPB2
XAIS2
MASK2
PWRDN2
8
1000
EQA3
EQB3
EQC3
LOOPA3
LOOPB3
XAIS3
MASK3
PWRDN3
9
1001
EQA4
EQB4
EQC4
LOOPA4
LOOPB4
XAIS4
MASK4
PWRDN4
10
1010
0
0
0
0
0
0
0
0
11
1011
0
CODE3
0
CODE4
0
0
0
0
12
1100
CODE1
CODE2
JABW0
(0)
PHIZALM
(0)
PRLALM
(0)
PFLALM
(0)
RCVAIS
(0)
ALTIMER
(0)
13
1101
0
0
0
0
0
0
0
0
14—15
1110—1111
RESERVED
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