參數(shù)資料
型號： TLIU04C1
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface(四T1/E1線接口)
中文描述： 四T1/E1線路接口（四個T1/E1線接口）
文件頁數(shù)： 5/100頁
文件大?。?/td> 1321K
代理商： TLIU04C1
Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
5
Lucent Technologies Inc.
List of Figures
Figures
Page
Figure 1. TLIU04C1 Microprocessor Mode Pin Diagram.......................................................................................... 9
Figure 2. TLIU04C1 Block Diagram, CMODE = 1 (Microprocessor Mode)............................................................ 18
Figure 3. Block Diagram of the Quad Line Interface Unit (Single Channel) ........................................................... 19
Figure 4. DS1/T1 Receiver Jitter Accommodation Without Jitter Attenuator.......................................................... 24
Figure 5. DS1/T1 Receiver Jitter Transfer Without Jitter Attenuator ...................................................................... 25
Figure 6. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator....................................................... 27
Figure 7. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator ................................................................... 28
Figure 8. DSX-1 Isolated Pulse Template .............................................................................................................. 31
Figure 9. ITU-T G.703 Pulse Template .................................................................................................................. 33
Figure 10. DS1/T1 Receiver Jitter Accommodation with Jitter Attenuator.............................................................. 37
Figure 11. DS1/T1 Jitter Transfer of the Jitter Attenuator....................................................................................... 38
Figure 12. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator........................................................... 39
Figure 13. CEPT/E1 Jitter Transfer of the Jitter Attenuator.................................................................................... 40
Figure 14. Line Termination Circuitry ..................................................................................................................... 50
Figure 15. Mode 1—Read Cycle Timing (MPMODE = 0, MPMUX = 0) ................................................................. 55
Figure 16. Mode 1—Write Cycle Timing (MPMODE = 0, MPMUX = 0) ................................................................. 55
Figure 17. Mode 2—Read Cycle Timing (MPMODE = 0, MPMUX = 1) ................................................................. 56
Figure 18. Mode 2—Write Cycle Timing (MPMODE = 0, MPMUX = 1) ................................................................. 56
Figure 19. Mode 3—Read Cycle Timing (MPMODE = 1, MPMUX = 0) ................................................................. 57
Figure 20. Mode 3—Write Cycle Timing (MPMODE = 1, MPMUX = 0) ................................................................. 57
Figure 21. Mode 4—Read Cycle Timing (MPMODE = 1, MPMUX = 1) ................................................................. 58
Figure 22. Mode 4—Write Cycle Timing (MPMODE = 1, MPMUX = 1) ................................................................. 58
Figure 23. Interface Data Timing (ACM = 0)........................................................................................................... 59
Figure 24. TLIU04C1 Direct Logic Control Mode Pin Diagram............................................................................... 61
Figure 25. TLIU04C1 Block Diagram, CMODE = 0 (Direct Logic Mode)................................................................ 67
Figure 26. Block Diagram of the Quad Line Interface Unit (Single Channel) ......................................................... 68
Figure 27. DS1/T1 Receiver Jitter Accommodation Without Jitter Attenuator........................................................ 73
Figure 28. DS1/T1 Receiver Jitter Transfer Without Jitter Attenuator .................................................................... 74
Figure 29. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator..................................................... 76
Figure 30. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator ................................................................. 77
Figure 31. DSX-1 Isolated Pulse Template............................................................................................................ 80
Figure 32. ITU-T G.703 Pulse Template ................................................................................................................ 81
Figure 33. DS1/T1 Receiver Jitter Accommodation with Jitter Attenuator.............................................................. 85
Figure 34. DS1/T1 Jitter Transfer of the Jitter Attenuator....................................................................................... 86
Figure 35. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator........................................................... 87
Figure 36. CEPT/E1 Jitter Transfer of the Jitter Attenuator.................................................................................... 88
Figure 37. Line Termination Circuitry ..................................................................................................................... 94
Figure 38. Interface Data Timing (ACM = 0)........................................................................................................... 97
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