參數(shù)資料
型號(hào)： ST72774S9T1
廠商： 意法半導(dǎo)體
元件分類： ADC
英文描述： 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述： 8位USB單片機(jī)的顯示器，高達(dá)60K章檢察官辦公室，每1000內(nèi)存，模數(shù)轉(zhuǎn)換器，定時(shí)器，同步，材質(zhì)單元，脈寬調(diào)制/的BRM，的H / W DDC的
文件頁數(shù)： 95/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1
ST72774/ST727754/ST72734
95/144
4.8 DDC INTERFACE (DDC)
4.8.1 Introduction
The DDC (Display Data Channel) Bus Interface is
mainly used by the monitor to identify itself to the
video controller, by the monitor manufacturer to
perform factory alignment, and by the user to
adjust the monitor’s parameters.
The DDC interface consists of two parts:
I
A
fully
hardware-implemented
DDC1
and
specification 3.0 compliant). It accesses the
ST7 on-chip memory directly through a built-in
DMA engine.
I
A second interface, supporting the slave I
2
C
functions for handling DDC/CI mode (DDC2Bi),
factory alignment or Enhanced DDC (EDDC) by
software.
interface,
(VESA
supporting
DDC2B
4.8.2 DDC Interface Features
4.8.2.1 Hardware DDC1/2B Interface Features
I
Full
hardware
support
communications (VESA specification versions 2
and 3)
I
Hardware detection of DDC2B addresses A0h/
A1h and optionally A2h/A3h (P&D) or A6h/A7h
(FPDI-2)
I
Separate mapping of EDID version 1 (128
bytes) and EDID version 2 (256 bytes) when
both must coexist
I
Support for error recovery mechanism
I
Detection of misplaced Start and Stop
conditions
for
DDC1/2B
I
I
2
C byte, random and sequential read modes
I
DMA transfer from any memory location and to
RAM
I
Automatic memory address incrementation
I
End of data downloading flag and interrupt
capability
4.8.2.2 DDC/CI - Factory Interface Features
General I
2
C Features:
– Parallel bus/I
2
C protocol converter
– Interrupt generation
– Standard I
2
C mode/Fast I
2
C mode
– 7-bit Addressing
I
2
C Slave Features:
– I
2
C bus busy flag
– Start bit detection flag
– Detection of misplaced Start or Stop condition
– Transfer problem detection
– Address Matched detection
– Programmable Address detection and/or
Hardware detection of Enhanced DDC (ED-
DC) addresses (60h/61h)
– End of byte transmission flag
– Transmitter/Receiver flag
– Stop condition Detection
Figure 56. DDC Interface Overview
SDAD
SCLD
VSYNCI
SDA
SCL
VSYNC
HARDWARE DDC1/2B
INTERFACE
I2C SLAVE
INTERFACE
(DDC/CI - Factory Alignment)
VSYNCI2
VSYNC2
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