參數(shù)資料
型號： ST72774S9T1
廠商： 意法半導(dǎo)體
元件分類： ADC
英文描述： 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述： 8位USB單片機(jī)的顯示器，高達(dá)60K章檢察官辦公室，每1000內(nèi)存，模數(shù)轉(zhuǎn)換器，定時(shí)器，同步，材質(zhì)單元，脈寬調(diào)制/的BRM，的H / W DDC的
文件頁數(shù)： 69/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1
ST72774/ST727754/ST72734
69/144
SYNC PROCESSOR (SYNC)
(Cont’d)
MUX CONTROL REGISTER (MCR)
Read/Write
Reset Value: 0010 0000 (20h)
Bit 7:6 =
BP1, BP0
Back Porch Pulse control
Bit 5 =
FBSEL
VSYNCO/HSYNCO or VFBACK/
HFBACK analysis
0: HFBACK & VFBACK
1: HSYNCO & VSYNCO
Bit 4 =
SCI0
HSYNCI/CSYNCI selection
0: HSYNCI
1: CSYNCI
Bit 3:2 =
HS1, HS0
Horizontal Signal selection
These bits allow inversion of the HSYNCI/CSYNCI
Note:
In case of composite sync, if HSYNCO blanking is
enabled (HINH=0 in the ENR register), HS1 must =
1 (CLAMPOUT after HSYNCO rising edge not al-
lowed).
Bit 1 =
VOP
Vertical Polarity control
The VOP bit inverts the VSYNCO Sync signal.
0: No polarity inversion (VSYNC0 <- VSYNCI)
1: Inversion enabled (VSYNC0 <- VSYNCI)
Note:
If at each vertical input capture the VPOL bit is cop-
ied by software on the VOP bit, the VSYNCO signal
will have a constant positive polarity.
Note:
The internally extracted VSYNCO has ALWAYS
negative polarity.
Bit 0 = Reserved. Must always be cleared.
7
0
BP1
BP0
FBSEL SCI0
HS1
HS0
VOP
-
BP1
0
0
1
1
BP0
0
1
0
1
Back Porch pulse width
No Back Porch, Moire output selected
167ns Back Porch ± 10 ns
333ns Back Porch ± 10 ns
666ns Back Porch ± 10 ns
HS1
HS0
HSYNCI Selection Mode
0
0
CLAMPOUT after HSYNCO rising edge
HSYNC0 <- (HSYNCI, CSYNCI)
0
1
CLAMPOUT after HSYNCO rising edge
HSYNC0 <- (HSYNCI, CSYNCI)
1
0
CLAMPOUT after HSYNCO falling edge
HSYNC0 <- (HSYNCI, CSYNCI)
1
1
CLAMPOUT after HSYNCO falling edge
HSYNC0 <- (HSYNCI,CSYNCI)
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