參數(shù)資料
型號(hào): ST72774S9T1
廠商: 意法半導(dǎo)體
元件分類: ADC
英文描述: 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述: 8位USB單片機(jī)的顯示器,高達(dá)60K章檢察官辦公室,每1000內(nèi)存,模數(shù)轉(zhuǎn)換器,定時(shí)器,同步,材質(zhì)單元,脈寬調(diào)制/的BRM,的H / W DDC的
文件頁數(shù): 63/144頁
文件大?。?/td> 1280K
代理商: ST72774S9T1
ST72774/ST727754/ST72734
63/144
SYNC PROCESSOR (SYNC)
(Cont’d)
4.4.6.5 Example of VSYNCO extraction for a
negative composite sync with serration pulses
Refer to
Figure 43
.
In extraction mode, the 5-bit comparator checks
the counter value with respect to the threshold.
When the incoming signal is high, the counter is
increased, otherwise it is decreased.
When the counter reaches the threshold on its way
down, VSYNCO is asserted. During the vertical
blanking, the counter value is decreased down to a
programmable minimum, i.e. it does not underflow.
When the vertical period is finished, the counter
starts counting up and when the maximum is
reached, VSYNCO is negated. The extracted
signal may be validated by software since it is input
to Timer ICAP1.
Serration pulses during vertical blanking can be
filtered if the serration pulse widths are less than
8μs.
In the same way, positive composite sync signals
can be used by properly selecting the edge
sensitivity in HSYNCI width measurement mode
(LCV0 bit).
Figure 43. VSYNCO Extraction from a Composite Signal (negative polarity)
Figure 44. Obtaining the 11-bit Vertical Period (V11BITS)
7
VGENR
VR01990
8μs
Composite signal
Input
Max Pulse width: 8μs
1F-Threshold
Counter value:
1F=Max
Serration pulses
VSYNCO Pulse
Max Delay: 8μs
or threshold
HSYNCO
Threshold
0=Min
VSYNCO
generated
7
0
0
0
10
CFGR
V11BITS
Example:
VGENR=CCh, CFGR = 3h
V11bits=663h
Q’2 Q’1 Q’0
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