參數(shù)資料
型號： ST72774S9T1
廠商： 意法半導(dǎo)體
元件分類： ADC
英文描述： 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述： 8位USB單片機(jī)的顯示器，高達(dá)60K章檢察官辦公室，每1000內(nèi)存，模數(shù)轉(zhuǎn)換器，定時器，同步，材質(zhì)單元，脈寬調(diào)制/的BRM，的H / W DDC的
文件頁數(shù)： 112/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1
ST72774/ST727754/ST72734
112/144
DDC INTERFACE
(Cont’d)
DDC STATUS REGISTER 2 (SR2)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:5 = Reserved. Forced to 0 by hardware.
Bit 4 =
AF
Acknowledge failure
.
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 =
STOPF
Stop detection.
This bit is set by hardware when a Stop condition is
detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
Bit 2 = Reserved. Forced to 0 by hardware.
Bit 1 =
BERR
Bus error.
This bit is set by hardware when the interface
detects a misplaced Start or Stop condition. An
interrupt is generated if ITE=1. It is cleared by
software reading SR2 register or by hardware
when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Bit 0 =
EDDCF
Enhanced DDC address detected.
This bit is set by hardware when the Enhanced
DDC address (60h/61h) is detected on the bus
while EDDCEN=1. It is cleared by hardware when
a Start or a Stop condition (STOPF=1) is detected,
or when the interface is disabled (PE=0).
0: No Enhanced DDC address detected on bus
1: Enhanced DDC address detected on bus
7
0
0
0
0
AF
STOPF
0
BERR
EDDC
F
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