參數(shù)資料
型號： ST72774S9T1
廠商： 意法半導(dǎo)體
元件分類： ADC
英文描述： 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述： 8位USB單片機的顯示器，高達(dá)60K章檢察官辦公室，每1000內(nèi)存，模數(shù)轉(zhuǎn)換器，定時器，同步，材質(zhì)單元，脈寬調(diào)制/的BRM，的H / W DDC的
文件頁數(shù)： 53/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1
ST72774/ST727754/ST72734
53/144
16-BIT TIMER
(Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
Bit 7 =
ICF1
Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred. To clear this
bit, first read the SR register, then read or
write the low byte of the IC1R (IC1LR) regis-
ter.
Bit 6 =
OCF1
Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then
read or write the low byte of the OC1R
(OC1LR) register.
Bit 5 =
TOF
Timer Overflow.
0: No timer overflow (reset value).
1:The free running counter rolled over from
FFFFh to 0000h. To clear this bit, first read
the SR register, then read or write the low
byte of the CR (CLR) register.
Note:
Reading or writing the ACLR register does not clear
TOF.
Bit 4 =
ICF2
Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred.To clear this
bit, first read the SR register, then read or
write the low byte of the IC2R (IC2LR) regis-
ter.
Bit 3 =
OCF2
Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then
read or write the low byte of the OC2R
(OC2LR) register.
Bit 2-0 = Unused.
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the
input capture 1 event).
OUTPUT
(OC1HR)
COMPARE 1 HIGH
REGISTER
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
OUTPUT
(OC1LR)
COMPARE
1
LOW
REGISTER
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
7
0
ICF1
OCF1
TOF
ICF2
OCF2
7
0
MSB
LSB
7
0
MSB
LSB
7
0
MSB
LSB
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