參數(shù)資料
型號(hào)： ST72774S9T1
廠商： 意法半導(dǎo)體
元件分類： ADC
英文描述： 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述： 8位USB單片機(jī)的顯示器，高達(dá)60K章檢察官辦公室，每1000內(nèi)存，模數(shù)轉(zhuǎn)換器，定時(shí)器，同步，材質(zhì)單元，脈寬調(diào)制/的BRM，的H / W DDC的
文件頁數(shù)： 56/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1
ST72774/ST727754/ST72734
56/144
4.4 SYNC PROCESSOR (SYNC)
4.4.1 Introduction
The Sync processor handles all the management
tasks of the video synchronization signals, and is
used with the timer and software to provide
information and status on the video standard and
timings. This block supports multiple video
standards such as: Separate Sync, Composite
Sync and (via an external extractor) Sync on
Green. The internal clock in the Sync processor is
4 MHz.
4.4.2 Main Features
I
Input Processing
– Presence of incoming signals (edge detection)
– Read the HSYNCI / VSYNCI input signal levels
– Measure the signal periods
– Detect the sync polarities
– Detect the composite sync and extract VSYNCO
I
Output Processing
– Control the sync output polarities
– Generate free-running frequencies
– Generate a video blanking signal
– Generate a clamping signal or a Moire signal
I
Analyzer Mode
– Measure the number of scan lines per frame to
simplify OSD vertical centering
– Detect HSYNCI reaching too high a frequency
– Detect pre/post equalization pulses
– Measure the low level of HSYNCO or HFBACK
I
Corrector Mode
– Inhibit Pre/Post equalization pulses
– Program VSYNCO pulse width extension
– Extend VSYNCO pulse widths during:
post-equalization pulse detection only
pre and post-equalization pulse detection
Note:
Some external pins are not available on all devices.
Refer to the device pinout description.
Figure 37. Sync Processor Block Diagram
Sync Generator
Sync Analyzer
Sync Corrector
Hardware Block
VSYNC Generator
40 - 200 Hz
Typical Pulse Width
20 - 256 μs
HSYNC Generator
15 - 200 kHz
Duty cycle range
3 - 40 %
Latch
00
match
Latch
1F
match
LCV0
Sync
&
Edge
Detect
Capture
Register
LD
V Sync O
Polarity
V Sync
Correction
1
Polarity
Detector
Pull-Up Resistor (if existing)
VSYNCI1
VSYNCO
1
0
HSYNCI2
CLAMPOUT
HSYNCO
ICAP1 TIMER
HVGEN
CSYNCI
CLPINV
1
0
LCV1
Vsync*
LCV1
Control
Logic
SCI0
ICAP2 TIMER
VSYNCI
HSYNCI / CSYNCI
PSCD
HVGEN
1
0
SYNOP
SYNOP
H Sync O
Polarity
H Sync O
Correction
H-Inhibit
ON/OFF
Back Porch
Clamp
Generator
Clamp
Polarity
Latch
Pulse Detect
Prescaler
V
S
Y
N
C
O
5-Bit Counter
CLK
EN
Up / Down
VR02071C
CLMPEN
0
VFBACK
1
0
FBSEL
FBSEL
00
Other
BP1, BP0
HFBACK
VFBACK
Latch
Pulse Detect
Latch
Pulse Detect
VSYNCI2
1
0
HVSEL
1
0
HVSEL
HSYNCI1
(Positive polarity)
HFBACK
Blanking
Generator
BLANKOUT
BLKEN
(seINT
Note:
CLK is f
INT/2
in fast mode (see note in Clock System section)
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