參數(shù)資料
型號： ST72774S9T1
廠商： 意法半導(dǎo)體
元件分類： ADC
英文描述： 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述： 8位USB單片機(jī)的顯示器，高達(dá)60K章檢察官辦公室，每1000內(nèi)存，模數(shù)轉(zhuǎn)換器，定時(shí)器，同步，材質(zhì)單元，脈寬調(diào)制/的BRM，的H / W DDC的
文件頁數(shù)： 93/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1
ST72774/ST727754/ST72734
93/144
I2C SINGLE MASTER BUS INTERFACE
(Cont’d)
I
2
C STATUS REGISTER 2 (SR2)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:5 = Reserved. Forced to 0 by hardware.
Bit 4 =
AF
Acknowledge failure
.
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
1: Acknowledge failure
Bit 3:0 = Reserved. Forced to 0 by hardware.
I
2
C CLOCK CONTROL REGISTER (CCR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 =
FM/SM
Fast/Standard I
2
C mode.
This bit is set and cleared by software.
It is not
cleared when the interface is disabled (PE=0).
0: Standard I
2
C mode
1: Fast I
2
C mode
Bit 6:0 =
CC6-CC0
7-bit clock divider.
These bits select the speed of the bus (F
SCL
)
depending on the I
2
C mode. They are not cleared
when the interface is disabled (PE=0).
– Standard mode (FM/SM=0): F
SCL
<= 100kHz
F
SCL
= F
CPU
/(2x([CC6..CC0]+2))
– Fast mode (FM/SM=1): F
SCL
> 100kHz
F
SCL
= F
CPU
/(3x([CC6..CC0]+2))
Note:
The programmed F
SCL
assumes no load on SCL
and SDA lines.
I
2
C DATA REGISTER
(
DR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:0 =
D7-D0
8-bit Data Register.
These bits contains the byte to be received or
transmitted on the bus.
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
ister.
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
nificant bit of the address.
Then, the next data bytes are received one by
one after reading the DR register.
7
0
0
0
0
AF
0
0
0
0
7
0
FM/SM
CC6
CC5
CC4
CC3
CC2
CC1
CC0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
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