參數(shù)資料
型號： ST72774S9T1
廠商： 意法半導體
元件分類： ADC
英文描述： 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述： 8位USB單片機的顯示器，高達60K章檢察官辦公室，每1000內存，模數(shù)轉換器，定時器，同步，材質單元，脈寬調制/的BRM，的H / W DDC的
文件頁數(shù)： 11/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1
ST72774/ST727754/ST72734
11/144
MEMORY MAP
(Cont’d)
Table 2. Hardware Register Memory Map
Address
Block
Register Label
Register Name
Reset
Status
Remarks
0000h
0001h
PADR
PADDR
Port A Data Register
Port A Data Direction Register
00h
00h
R/W
R/W
0002h
0003h
PBDR
PBDDR
Port B Data Register
Port B Data Direction Register
00h
00h
R/W
R/W
0004h
0005h
PCDR
PCDDR
Port C Data Register
Port C Data Direction Register
00h
00h
R/W
R/W
0006h
0007h
PDDR
PDDDR
Port D Data Register
Port D Data Direction Register
00h
00h
R/W
R/W
0008h
Watchdog
WDGCR
Watchdog Control Register
7Fh
R/W
0009h
MISCR
Miscellaneous Register
10h
R/W
000Ah
000Bh
ADC
ADCDR
ADCCSR
ADC Data Register
ADC Control Status register
00h
00h
Read only
R/W
000Ch
000Dh
DDC1/2B
DDCDCR
DDCAHR
DDC1/2B Control Register
DDC1/2B Address Pointer High Register
00h
xxh
R/W
R/W
000Eh
000Fh
00010h
TMU
TMUCSR
TMUT1CR
TMUT2CR
TMU control status register
TMU T1 counter register
TMU T2 counter register
FCh
FFh
FFh
R/W
Read only
Read only
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
Timer
TIMCR2
TIMCR1
TIMSR
TIMIC1HR
TIMIC1LR
TIMOC1HR
TIMOC1LR
TIMCHR
TIMCLR
TIMACHR
TIMACLR
TIMIC2HR
TIMIC2LR
TIMOC2HR
TIMOC2LR
Timer Control Register 2
Timer Control Register 1
Timer Status Register
Timer Input Capture 1 High Register
Timer Input Capture 1 Low Register
Timer Output Compare 1 High Register
Timer Output Compare 1 Low Register
Timer Counter High Register
Timer Counter Low Register
Timer Alternate Counter High Register
Timer Alternate Counter Low Register
Timer Input Capture 2 High Register
Timer Input Capture 2 Low Register
Timer Output Compare 2 High Register
Timer Output Compare 2 Low Register
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read only
Read only
Read only
R/W
R/W
Read only
R/W
Read only
R/W
Read only
Read only
R/W
R/W
0020h
to
0024h
Reserved Area (5 bytes)
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