參數(shù)資料
型號： ST72774S9T1
廠商： 意法半導(dǎo)體
元件分類： ADC
英文描述： 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述： 8位USB單片機(jī)的顯示器，高達(dá)60K章檢察官辦公室，每1000內(nèi)存，模數(shù)轉(zhuǎn)換器，定時器，同步，材質(zhì)單元，脈寬調(diào)制/的BRM，的H / W DDC的
文件頁數(shù)： 72/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1
ST72774/ST727754/ST72734
72/144
SYNC PROCESSOR (SYNC)
(Cont’d)
HORIZONTAL SYNC GENERATOR REGISTER
(HGENR)
Read/Write
Reset Value: 0000 0000 (00h)
Case HVGEN = 1:
Generation mode
In this mode, this register contains the Hsync free-
running frequency.
The generated signal is:
- Pulse width: 2 μs.
- Period PH = ((HGENR+1)/4) μs.
- Polarity: Positive
Note:
The value in HGENR must be in the range [8..255].
Case HVGEN = 0:
Analyzer/corrector Mode
Sub-case HACQ = 1
: Analyzer Mode
By setting HACQ bit by software the Analyzer
mode starts. When HACQ is cleared by hardware,
HGENR returns the duration of HSYNCO/
HFBACK low level. The analysis should be done
before corrector mode.
Sub-case HACQ = 0:
Corrector Mode
In this mode, the final HSYNCO signal on the pin
can be corrected in order to detect and inhibit pre/
post equalization pulses.
VERTICAL SYNC GENERATOR REGISTER
(VGENR)
Read/Write
Reset Value: 0000 0000 (00h)
Case HVGEN = 1
: Generation mode
In this mode, this register contains the Vsync free-
running frequency (11-bit value).
The generated signal is:
- Pulse width: 4 * PH μs (horizontal period).
- Period PV = PH * (V11bits) μs.
- Polarity: Positive
Note:
The value in VGENR must be in the range [5..255]
The Vsync generation mode works as an 11-bit hor-
izontal line counter (2047 scan lines per frame
max.). The 3 LSB are in the CFGR register. Refer
to
Figure 44
.
Case HVGEN = 0:
Analyzer/Corrector Mode
Sub-case VACQ = 1:
Analyzer Mode
Set the VACQ bit to start analyzer mode. When
VACQ is cleared by hardware, VGENR/CFGR
returns the number of scan lines during the
VSYNCO/VFBACK low level period.
Sub-case VACQ = 0:
Corrector Mode
VSYNCO pulse width is extended by VGENR scan
lines. If VGENR = 0, all VSYNCO corrections are
disabled.
7
0
MSB
LSB
7
0
MSB
LSB
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