參數(shù)資料
型號： ST72774S9T1
廠商： 意法半導(dǎo)體
元件分類： ADC
英文描述： 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述： 8位USB單片機(jī)的顯示器，高達(dá)60K章檢察官辦公室，每1000內(nèi)存，模數(shù)轉(zhuǎn)換器，定時(shí)器，同步，材質(zhì)單元，脈寬調(diào)制/的BRM，的H / W DDC的
文件頁數(shù)： 88/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1
ST72774/ST727754/ST72734
88/144
I2C SINGLE MASTER BUS INTERFACE
(Cont’d)
Acknowledge may be enabled and disabled by
software.
The speed of the I
2
C interface may be selected
between Standard (0-100KHz) and Fast I
2
C (100-
400KHz).
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the
microcontroller to write the byte in the Data
Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
The SCL frequency (F
scl
) is controlled by a
programmable clock divider which depends on the
I
2
C bus mode.
When the I2C cell is enabled, the SDA and SCL
ports must be configured as floating open-drain
output or floating input. In this case, the value of
the external pull-up resistance used depends on
the application.
When the I2C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
Figure 53. I
2
C Interface Block Diagram
DATA REGISTER (DR)
DATA SHIFT REGISTER
CLOCK CONTROL REGISTER (CCR)
STATUS REGISTER 1 (SR1)
CONTROL REGISTER (CR)
SDAI
SCLI
CONTROL LOGIC
STATUS REGISTER 2 (SR2)
INTERRUPT
CLOCK CONTROL
DATA CONTROL
SCL
SDA
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