參數(shù)資料
型號： ST72774S9T1
廠商： 意法半導(dǎo)體
元件分類： ADC
英文描述： 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述： 8位USB單片機(jī)的顯示器，高達(dá)60K章檢察官辦公室，每1000內(nèi)存，模數(shù)轉(zhuǎn)換器，定時器，同步，材質(zhì)單元，脈寬調(diào)制/的BRM，的H / W DDC的
文件頁數(shù)： 70/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1
ST72774/ST727754/ST72734
70/144
SYNC PROCESSOR (SYNC)
(Cont’d)
COUNTER CONTROL REGISTER (CCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 =
PSCD
Prescaler Enable bit.
0: Enable the Prescaler by 256
1: Disable the Prescaler and reset it to 7Fh. This
also disables the ICAP2 event.
Bit 6:5 =
LCV1, LCV0
VSYNCO Extraction Control
Bit 4:0 =
CV4-CV0
Counter Captured Value.
These bits contain the counter captured value in
different modes.
In VSYNCO extraction mode, they contain the
HSYNCI pulse-width measurement.
POLARITY REGISTER (POLR)
Bits 5-4 Read Only, other bits Read/Write
Reset Value: 0000 1000 (08h)
Bit 7 =
SOG
Sync On Green Detector
SOG is set by hardware if CSYNCI pulse is not
included in the window between HSYNCI rising
edge and HSYNCI falling edge + dt .
Cleared by software.
Table 19. Sync On Green Window
Bit 6 = Reserved, forced by hardware to 0.
Bit 5 =
VPOL
Vertical Sync polarity
(read only)
0: Positive polarity
1: Negative polarity
Note:
If the Vertical Sync polarity is changing, the VPOL
bit will be updated after a typical delay of 4 msec.
Bit 4 =
2FHDET
Detection of Pre/Post Equalization
pulses
(read only).
This bit is continuously updated by hardware. It is
valid when the sync generator and horizontal
analyzer are disabled (HVGEN = 0, HACQ = 0).
0: None detected
1: Pre/Post Equalization pulses detected
Bit 3 =
HVSEL
Alternate Sync Input Select.
This bit selects between the two sets of Horizontal
and Vertical Sync inputs
0: HSYNCI2 / VSYNCI2
1: HSYNCI1 / VSYNCI1
Bit 2 =
VCORDIS
Extension Disable Signal
(Extension with VGENR Register)
0: enable
1: disable
Bit 1 =
CLPINV
Programmable ClampOut pulse
polarity.
0: Positive
1: Negative
Bit 0 =
BLKINV
Programmable blanking polarity
0: Negative
1: Positive
7
0
PSCD
LCV1
LCV0
CV4 CV3 CV2 CV1
CV0
LCV1
LCV0
VSYNC0 Control Bits
Normal mode
Counter capture on input falling edge
Normal mode
Counter capture on input rising edge
Extraction mode
CSYNCI/HSYNCI Negative polarity
CV4-0 = counter minimum threshold
Extraction mode
CSYNCI/HSYNCI Positive polarity
CV4-0 = counter maximum threshold
0
0
0
1
1
0
1
1
7
0
SOG
0
VPOL 2FHDET HVSEL VCORDIS CLPINV BLKINV
WINDOW DELAY
min.
max.
dt
165 ns
250 ns
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