參數(shù)資料
型號： ST72774S9T1
廠商： 意法半導體
元件分類： ADC
英文描述： 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述： 8位USB單片機的顯示器，高達60K章檢察官辦公室，每1000內(nèi)存，模數(shù)轉換器，定時器，同步，材質(zhì)單元，脈寬調(diào)制/的BRM，的H / W DDC的
文件頁數(shù)： 71/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1
ST72774/ST727754/ST72734
71/144
SYNC PROCESSOR (SYNC)
(Cont’d)
LATCH REGISTER (LATR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 =
CSYN
Detection of pulses on CSYNCI
Set on falling edge of CSYNCI
Cleared by software (by writing zero).
Bit 6 =
HSYN
Detection of pulses on HSYNCI
Set on falling edge of HSYNCI1 or HSYNCI2
Cleared by software (by writing zero).
Bit 5 =
VSYN
Detection of pulses on VSYNCI
Set on falling edge of VSYNCI1 or VSYNCI2
Cleared by software (by writing zero).
Bit 4 =
HFLY
Detection of pulses on HFBACK
Set on falling edge of HFBACK input
Cleared by software (by writing zero).
Bit 3 =
VFLY
Detection of pulses on VFBACK
Set on falling edge of VFBACK input
Cleared by software (by writing zero).
Bit 2 =
UPLAT
Detection of the maximum value of
5-bit up/down counter.
Set when the 5 bit up/down counter reaches its
maximum value (1Fh or Threshold)
Cleared by software (by writing zero).
Bit 1 =
DWNLAT
Detection of minimum value of 5-
bit up/down counter.
Set when the 5 bit up/down counter reaches its
minimum value (00 or Threshold)
Cleared by software (by writing zero).
Note:
DWNLAT and UPLAT may be used for HSYNCI po-
larity detection and Composite Sync detection as
follows:
Bit 0 =
2FHLAT
equalization pulses latch.
This bit may be used to detect pre/
postequalization pulses or a too high horizontal
frequency.
Set by hardware when Pre/Post equalization
pulses are detected.
Must be reset by software.
It is valid when the sync generator and Horizontal
analyzer are disabled (HVGEN = 0, HACQ = 0)
7
0
CSYN HSYN VSYN HFLY VFLY UPLAT DWNLAT 2FHLAT
UPLAT
0
0
1
1
DWNLAT
0
1
0
1
HSYNCI Characteristics
No Info
Positive Polarity
Negative Polarity
Composite Sync
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