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參數(shù)資料
| 型號(hào)： | ST72774S9T1 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類(lèi)： | ADC |
| 英文描述： | 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C |
| 中文描述： | 8位USB單片機(jī)的顯示器，高達(dá)60K章檢察官辦公室，每1000內(nèi)存，模數(shù)轉(zhuǎn)換器，定時(shí)器，同步，材質(zhì)單元，脈寬調(diào)制/的BRM，的H / W DDC的 |
| 文件頁(yè)數(shù)： | 41/144頁(yè) |
| 文件大?。?/td> | 1280K |
| 代理商： | ST72774S9T1 |
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4.3 16-BIT TIMER (TIM)
4.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input
signals (input capture) or generation of up to two
output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be
modulated from a few microseconds to several
milliseconds using the timer prescaler and the
CPU clock prescaler.
4.3.2 Main Features
I
Programmable prescaler: f
cpu
divided by 2, 4 or
8.
I
Overflow status flag and maskable interrupt
I
External clock input (must be at least 4 times
slower than the CPU
clock speed) with the
choice of active edge
I
Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
I
Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
I
Pulse width modulation mode (PWM)
I
One pulse mode
I
5 alternate functions on I/O ports*
The Block Diagram is shown in
Figure 27
.
Note:
Some external pins are not available on all devices.
Refer to the device pin out description.
4.3.3 Functional Description
4.3.3.1 Counter
The principal block of the Programmable Timer is a
16-bit free running counter and its associated 16-
bit registers:
Counter Registers
– Counter High Register (CHR) is the most sig-
nificant byte (MSB).
– Counter Low Register (CLR) is the least sig-
nificant byte (LSB).
Alternate Counter Registers
– Alternate Counter High Register (ACHR) is the
most significant byte (MSB).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LSB).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note
page 43
).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in
Table 15 Clock
Control Bits
. The value in the counter register
repeats every 131.072, 262.144 or 524.288
internal processor clock cycles depending on the
CC1 and CC0 bits.
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