參數(shù)資料
型號： ST72774S9T1
廠商： 意法半導體
元件分類： ADC
英文描述： 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述： 8位USB單片機的顯示器，高達60K章檢察官辦公室，每1000內存，模數(shù)轉換器，定時器，同步，材質單元，脈寬調制/的BRM，的H / W DDC的
文件頁數(shù)： 75/144頁
文件大?。?/td> 1280K
代理商： ST72774S9T1
ST72774/ST727754/ST72734
75/144
4.5 TIMING MEASUREMENT UNIT (TMU)
4.5.1 Introduction
The timing measurement unit (TMU) allows the
analysis of the current video timing characteristics
in order to control display position and size.
It consists of measuring the timing between the
horizontal or vertical sync output signals and the
active video signal input (AV).
4.5.2 Main Features
I
Horizontal or vertical timing measurement
I
Oscillator clock f
OSC
(24 or 12 MHz) used for
horizontal measurement
I
Horizontal sync signal (HSYNCO or HFBACK)
and Vertical sync signal (VSYNCO or VFBACK)
used for all measurements
I
Measurements performed on positive signals
only
I
11-bit counter
I
Overflow detection
4.5.3 Functional Description
The Timing Measurement Unit is centered around
an 11-bit counter. Depending on the H_V bit of the
control register, the TMU measures the horizontal
or vertical video characteristics.
For horizontal analysis (refer to
Figure 48
):
– Obtain the minimum number of oscillator clock
cycles (H1) between the falling edge of the
horizontal sync signal (HSYNCO or HFBACK)
and the first rising edge of the active video in-
put (AV), for all lines, between 2 consecutive
vertical sync pulses.
– Obtain the minimum number of oscillator clock
cycles (H2) between the last falling edge of
the active video input (AV) and the rising edge
of the horizontal sync signal (HSYNCO or HF-
BACK) for all lines, between 2 consecutive
vertical sync pulses.
Note:
Horizontal measurement is inhibited during the high
level of VSYNCO or VFLYBACK.
For vertical analysis (refer to
Figure 49
):
– Obtain the minimum number of horizontal
sync pulses (V1) between the falling edge of
the vertical sync signal (VSYNCO or VF-
BACK) and the first rising edge of the active
video input, during 2 consecutive frames.
Figure 47. TMU Block Diagram
ST7 INTERNAL BUS
TMUT1CR
T1[7:0]
TMUT2CR
T2[7:0]
TMUCSR
11 bit COUNTER
11
8
8
3
3
T2[9] T2[8]
T1[9]
T1[8]
START
H_V
CONTROL
Clock
Start
Stop
HSYNCO or HFBACK
(1)
VSYNCO or VFBACK
(1)
AV
f
OSC
T2[10]
T1[10]
COMPARATOR
SUP
(FROM SYNC PROCESSOR)
Note 1:
Selection between Sync outputs or Flyback inputs is made in MISCR register (bit 6: FLY_SYN)
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