參數(shù)資料
型號： PCI1620GHK
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 71/164頁
文件大?。?/td> 720K
代理商： PCI1620GHK
4
–
3
4.4
Command Register
The PCI command register provides control over the PCI1620 interface to the PCI bus. All bit functions adhere to the
definitions in the
PCI Local Bus Specification
(see Table 4
–
2). None of the bit functions in this register are shared
among the PCI1620 PCI functions. Three command registers exist in the PCI1620, one for each function. Software
manipulates the PCI1620 functions as separate entities when enabling functionality through the command register.
The SERR_EN and PERR_EN enable bits in this register are internally wired OR between the three functions, and
these control bits appear to software to be separate for each function.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Command
Type
R
R
R
R
R
R
R
RW
R
RW
RW
R
R
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Command
04h
Read-only, Read/Write
0000h
Table 4
–
2. Command Register Description
BIT
SIGNAL
TYPE
FUNCTION
15
–
10
RSVD
R
Reserved. Bits 15
–
10 return 0s when read.
9
FBB_EN
R
Fast back-to-back enable. The PCI1620 does not generate fast back-to-back transactions; therefore, this
bit is read-only. This bit returns a 0 when read.
8
SERR_EN
RW
System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR
can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set
for the PCI1620 to report address parity errors.
0 = Disables the SERR output driver (default)
1 = Enables the SERR output driver
7
STEP_EN
R
Address/data stepping control. The PCI1620 does not support address/data stepping, and this bit is
hardwired to 0. Writes to this bit have no effect.
6
PERR_EN
RW
Parity error response enable. This bit controls the PCI1620 response to parity errors through the PERR
signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated by
asserting SERR.
0 = PCI1620 ignores detected parity errors (default).
1 = PCI1620 responds to detected parity errors.
5
VGA_EN
RW
VGA palette snoop. When set to 1, palette snooping is enabled (i.e., the PCI1620 does not respond to palette
register writes and snoops the data). When the bit is 0, the PCI1620 treats all palette accesses like all other
accesses.
4
MWI_EN
R
Memory write-and-invalidate enable. This bit controls whether a PCI initiator device can generate memory
write-and-invalidate commands. The PCI1620 controller does not support memory write-and-invalidate
commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. This bit returns
0 when read. Writes to this bit have no effect.
3
SPECIAL
R
Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The PCI1620 does
not respond to special cycle operations; therefore, this bit is hardwired to 0. This bit returns 0 when read.
Writes to this bit have no effect.
2
MAST_EN
RW
Bus master control. This bit controls whether or not the PCI1620 can act as a PCI bus initiator (master). The
PCI1620 can take control of the PCI bus only when this bit is set.
0 = Disables the PCI1620 ability to generate PCI bus accesses (default)
1 = Enables the PCI1620 ability to generate PCI bus accesses
1
MEM_EN
RW
Memory space enable. This bit controls whether or not the PCI1620 can claim cycles in PCI memory space.
0 = Disables the PCI1620 response to memory space accesses (default)
1 = Enables the PCI1620 response to memory space accesses
0
IO_EN
RW
I/O space control. This bit controls whether or not the PCI1620 can claim cycles in PCI I/O space.
0 = Disables the PCI1620 from responding to I/O space accesses (default)
1 = Enables the PCI1620 to respond to I/O space accesses
相關(guān)PDF資料
PDF描述
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
PCI9054AB50BI Interface IC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCI1620PDV 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PC Card Flash & Smart Card Cntrlr RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PCI-1620U 制造商:ADVANTECH 制造商全稱:Advantech Co., Ltd. 功能描述:8-port RS-232 PCI Communication Card, with Surge Protection
PCI1620ZHK 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PC Card Flash & Smart Card Cntrlr RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PCI-1622A-BE 制造商:Advantech Co Ltd 功能描述:8PORT RS-422/485 PCI COM CARD - Trays 制造商:Advantech Co Ltd 功能描述:8-port RS-422/485 UPCI COMM card
PCI-1622CU 制造商:ADVANTECH 制造商全稱:Advantech Co., Ltd. 功能描述:8-port RS-422/485 Universal PCI Communication Card with Isolation & EFT Protection
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*