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參數(shù)資料
| 型號： | PCI1620GHK |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 62/164頁 |
| 文件大?。?/td> | 720K |
| 代理商： | PCI1620GHK |
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3
–
20
Table 3
–
13. Interrupt Pin Register Cross Reference
INTRTIE BIT
INTPIN
FUNCTION 0
FUNCTION 1
0
01h
02h
1
01h
01h
3.6.5
Using Serialized IRQSER Interrupts
The serialized interrupt protocol implemented in the PCI1620 uses a single terminal to communicate all interrupt
status information to the host controller. The protocol defines a serial packet consisting of a start cycle, multiple
interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The packet data
describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and INTD. For details on
the IRQSER protocol, refer to the document
Serialized IRQ Support for PCI Systems
.
3.6.6
SMI Support in the PCI1620
The PCI1620 provides a mechanism for interrupting the system when power changes have been made to the PC
Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI) scheme.
SMI interrupts are generated by the PCI1620, when enabled, after a write cycle to either the socket control register
(CB offset 10h, see Section 6.5) of the CardBus register set, or the ExCA power control register (ExCA offset
02h/42h/802h, see Section 5.3) causes a power cycle change sequence to be sent on the power switch interface.
The SMI control is programmed through three bits in the system control register (PCI offset 80h, see Section 4.31).
These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 3
–
14 describes the SMI control
bits function.
Table 3
–
14. SMI Control
BIT NAME
FUNCTION
SMIROUTE
This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2.
SMISTAT
This socket dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1.
SMIENB
When set, SMI interrupt generation is enabled. This bit is shared by functions 0 and 1.
If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC on a per-socket basis. The CSC interrupt
can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control register (ExCA offset
1Eh/5Eh/81Eh, see Section 5.20).
If IRQ2 is selected by SMIROUTE, then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data
slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either
MFUNC3 or MFUNC6 through the multifunction routing register (PCI offset 8Ch, see Section 4.38).
3.7
Power Management Overview
In addition to the low-power CMOS technology process used for the PCI1620, various features are designed into the
device to allow implementation of popular power-saving techniques. These features and techniques are discussed
in this section.
3.7.1
Integrated Low-Dropout Voltage Regulator (LDO-VR)
The PCI1620 requires 1.8-V core voltage. The core power can be supplied by the PCI1620 itself using the internal
LDO-VR
. The core power can alternatively be supplied by an external power supply through the VR_OUT terminal.
Table 3
–
15 lists the requirements for both the internal core power supply and the external core power supply.
Table 3
–
15. Requirements for Internal/External 2.5-V Core Power Supply
SUPPLY
VCC
3.3 V
VR_EN
VR_OUT
NOTE
Internal 1.8-V LDO-VR is enabled. A 1.0
μ
F bypass capacitor is required on the VR_PORT
terminal for decoupling. This output is not for external use.
Internal
GND
1.8-V output
External
3.3 V
VCC
1.8-V input
Internal 1.8-V LDO-VR is disabled. An external 1.8-V power supply, of minimum 50-mA
capacity, is required. A 0.1
μ
F bypass capacitor on the VR_OUT terminal is required.
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