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參數(shù)資料
| 型號(hào)： | PCI1620GHK |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 68/164頁 |
| 文件大小： | 720K |
| 代理商： | PCI1620GHK |
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3
–
26
3.7.11 Master List of PME Context Bits and Global Reset-Only Bits
If the PME enable bit (bit 8) of the power-management control/status register (PCI offset A4h, see section 4.46) is
asserted, then the assertion of PRST will not clear the following PME context bits. If the PME enable bit is not asserted,
then the PME context bits are cleared with PRST. The PME context bits are:
Bridge control register (PCI offset 3Eh, see Section 4.25): bit 6
System control register (PCI offset 80h, see Section 4.31): bits 10, 9, 8
Power-management control/status register (PCI offset A4h, see Section 4.46): bits 15, 8
ExCA power control register (ExCA offset 802h, see Section 5.3): bits 7, 5
, 4
–
3, 1
–
0 (
82365SL mode only)
ExCA interrupt and general control register (ExCA offset 803h, see Section 5.4): bits 6
–
5
ExCA card status change register (ExCA offset 804h, see Section 5.5): bits 11
–
8, 3
–
0
ExCA card status-change-interrupt configuration register (ExCA offset 805h, see Section 5.6): bits 3
–
0
Socket event register (CardBus offset 00h, see Section 6.1): bits 3
–
0
Socket mask register (CardBus offset 04h, see Section 6.2): bits 3
–
0
Socket present state register (CardBus offset 08h, see Section 6.3): bits 13
–
7, 5
–
1
CardBus socket control register (CardBus offset 10h, see Section 6.5): bits 6
–
4, 2
–
0
Global reset places all registers in their default state regardless of the state of the PME enable bit. The GRST signal
is gated only by the SUSPEND signal. This means that assertion of SUSPEND blocks the GRST signal internally,
thus preserving all register contents. The registers cleared only by GRST are:
Status register (PCI offset 06h, see Section 4.5): bits 15
–
11, 8
Secondary status register (PCI offset 16h, see Section 4.14): bits 15
–
11, 8
Interrupt pin register (PCI offset 3Dh, see Section 4.24): bits 1,0 (function 1 only)
Subsystem vendor ID register (PCI offset 40h, see Section 4.26): bits 15
–
0
Subsystem ID register (PCI offset 42h, see Section 4.27): bits 15
–
0
PC Card 16-bit legacy mode base address register (PCI offset 44h, see Section 4.28): bits 31
–
1
System control register (PCI offset 80h, see Section 4.31): bits 31
–
29, 27
–
13, 11, 6
–
0
General-purpose event status register (PCI offset 88h, see Section 4.34): bits 15
–
14
General-purpose event enable register (PCI offset 89h, see Section 4.35): bits 15
–
14, 11, 8, 4
–
0
General-purpose output (PCI offset 8Bh, see Section 4.37): bits 4
–
0
Multifunction routing status register (PCI offset 8Ch, see Section 4.38): bits 27
–
0
Retry status register (PCI offset 90h, see Section 4.39): bits 7
–
5, 3, 1
Card control register (PCI offset 91h, see Section 4.40): bits 7
–
5, 2
–
0
Device control register (PCI offset 92h, see Section 4.41): bits 7
–
5, 3
–
0
Diagnostic register (PCI offset 93h, see Section 4.42): bits 7
–
0
Power management capabilities register (PCI offset A2h, see Section 4.45): bit 15
Serial bus data (PCI offset B0h, see Section 4.49): bits 7
–
0
Serial bus index (PCI offset B1h, see Section 4.50): bits 7
–
0
Serial bus slave address register (PCI offset B2h, see Section 4.51): bits 7
–
0
Serial bus control/status register (PCI offset B3h, see Section 4.52): bits 7, 5
–
0
ExCA identification and revision register (ExCA offset 00h, see Section 5.1): bits 7
–
0
ExCA global control register (ExCA offset 1Eh, see Section 5.20): bits 2
–
0
Socket present state register (CardBus offset 08h, see Section 6.3): bit 29
Socket power management register (CardBus offset 20h, see Section 6.6): bits 25
–
24
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PDF描述 |
|---|---|
| PCI1620PDV | Controller Miscellaneous - Datasheet Reference |
| PCI2050A | 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge |
| PCI2050GHK | BUS CONTROLLER |
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