參數(shù)資料
型號: PCI1620GHK
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 31/164頁
文件大小: 720K
代理商: PCI1620GHK
2
15
Table 2
9. PCI Interface Control Terminals
TERMINAL
NAME
NO.
I/O
DESCRIPTION
PDV
GHK
DEVSEL
198
F07
I/O
PCI device select. The PCI1620 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator
on the bus, the PCI1620 monitors DEVSEL until a target responds. If no target responds before timeout
occurs, then the PCI1620 terminates the cycle with an initiator abort.
FRAME
194
E08
I/O
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus
transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is
deasserted, the PCI bus transaction is in the final data phase.
GNT
169
B13
I
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1620 access to the PCI bus after the
current data transaction has completed. GNT may or may not follow a PCI bus request, depending on the PCI
bus parking algorithm.
IDSEL
183
E10
I
Initialization device select. IDSEL selects the PCI1620 during configuration space accesses. IDSEL can be
connected to one of the upper 24 PCI address lines
on the PCI bus.
IRDY
196
B07
I/O
PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the
transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted.
Until IRDY and TRDY are both sampled asserted, wait states are inserted.
PERR
201
E07
I/O
PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match
PAR when PERR is enabled through bit 6 of the command register (PCI offset 04h, see Section 4.4).
REQ
170
A13
O
PCI bus request. REQ is asserted by the PCI1620 to request access to the PCI bus as an initiator.
SERR
202
C06
O
PCI system error. SERR is an output that is pulsed from the PCI1620 when enabled through bit 8 of the
command register (PCI offset 04h, see Section 4.4), indicating a system error has occurred. The PCI1620
need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the command register,
this signal also pulses, indicating that an address parity error has occurred on a CardBus interface.
STOP
200
B06
I/O
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus
transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not
support burst data transfers.
TRDY
197
C07
I/O
PCI target ready. TRDY indicates the ability of the primary bus target to complete the current data phase of
the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted.
Until both IRDY and TRDY are asserted, wait states are inserted.
Care must be exercised in selection of the address line that is used for connecting to IDSEL. Check each PCI component to avoid the use of
address lines that it may have reserved, because address lines used can vary from one device to another of the same device type. For example,
one commonly-used chipset uses lines AD11 and AD12, and assignment of IDSEL to either of those lines in an implementation using that chipset
would result in an address conflict.
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