參數(shù)資料
型號： PCI1620GHK
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 129/164頁
文件大?。?/td> 720K
代理商： PCI1620GHK
5
–
23
5.20 ExCA Global Control Register
This register controls both PC Card sockets, and is not duplicated for each socket. The host interrupt mode bits in
this register are retained for 82365SL-DF compatibility. See Table 5
–
15 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Name
ExCA global control
Type
R
R
R
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
Register:
Offset:
ExCA global control
CardBus Socket Address + 81Eh:
Card A ExCA Offset 1Eh
Card B ExCA Offset 5Eh
Type:
Default:
Read-only, Read/Write
00h
Table 5
–
15. ExCA Global Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
7
–
5
RSVD
R
These bits return 0s when read. Writes have no effect.
4
INTMODEB
RW
Level/edge interrupt mode select, card B. This bit selects the signaling mode for the PCI1620 host interrupt
for card B interrupts. This bit is encoded as:
0 = Host interrupt is edge mode (default).
1 = Host interrupt is level mode.
Level/edge interrupt mode select, card A. This bit selects the signaling mode for the PCI1620 host interrupt
for card A interrupts. This bit is encoded as:
0 = Host interrupt is edge-mode (default).
1 = Host interrupt is level-mode.
Interrupt flag clear mode select. This bit selects the interrupt flag clear mechanism for the flags in the ExCA
card status change register. This bit is encoded as:
0 = Interrupt flags cleared by read of CSC register (default)
1 = Interrupt flags cleared by explicit writeback of 1
Card status change level/edge mode select. This bit selects the signaling mode for the PCI1620 host
interrupt for card status changes. This bit is encoded as:
0 = Host interrupt is edge-mode (default).
1 = Host interrupt is level-mode.
Power-down mode select. When the bit is set to 1, the PCI1620 is in power-down mode. In power-down
mode the PCI1620 card outputs are placed in a high-impedance state until an active cycle is executed on
the card interface. Following an active cycle the outputs are again placed in a high-impedance state. The
PCI1620 still receives functional interrupts and/or card status change interrupts; however, an actual card
access is required to wake up the interface. This bit is encoded as:
0 = Power-down mode disabled (default)
1 = Power-down mode enabled
3
INTMODEA
RW
2
IFCMODE
RW
1
CSCMODE
RW
0
PWRDWN
RW
相關(guān)PDF資料
PDF描述
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
PCI9054AB50BI Interface IC
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