- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369950 > PCI1620GHK Controller Miscellaneous - Datasheet Reference PDF資料下載
參數(shù)資料
| 型號： | PCI1620GHK |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 105/164頁 |
| 文件大小： | 720K |
| 代理商： | PCI1620GHK |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁當(dāng)前第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁
4
–
37
4.52 Serial Bus Control/Status Register
The serial bus control and status register communicates serial bus status information and selects the quick command
protocol. Bit 5 (REQBUSY) in this register must be polled during serial bus byte reads to indicate when data is valid
in the serial bus data register. See Table 4
–
24 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Serial bus control/status
Type
RW
R
R
R
RW
RW
RC
RC
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Serial bus control/status
B3h (function 0)
Read-only, Read/Write, Read/Clear
00h
Table 4
–
24. Serial Bus Control/Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
7
PROT_SEL
RW
Protocol select. When bit 7 is set, the send-byte protocol is used on write requests and the receive-byte
protocol is used on read commands. The word address byte in the serial bus index register (see
Section 4.50) is not output by the PCI1620 when bit 7 is set.
6
RSVD
R
Reserved. Bit 6 returns 0 when read.
5
REQBUSY
R
Requested serial bus access busy. Bit 5 indicates that a requested serial bus access (byte read or write)
is in progress. A request is made, and bit 5 is set, by writing to the serial bus slave address register (see
Section 4.51). Bit 5 must be polled on reads from the serial interface. After the byte read access has been
completed, this bit is cleared and the read data is valid in the serial bus data register.
4
ROMBUSY
R
Serial EEPROM busy status. Bit 4 indicates the status of the PCI1620 serial EEPROM circuitry. Bit 4 is set
during the loading of the subsystem ID and other default values from the serial bus EEPROM.
0 = Serial EEPROM circuitry is not busy
1 = Serial EEPROM circuitry is busy
3
SBDETECT
RW
Serial bus detect. When bit 3 is set, it indicates that the serial bus interface is detected and the MFUNC1
and MFUNC4 terminals are reconfigured as SDA and SCL. A pulldown resistor on the LATCH terminal
causes this bit to be set. This bit can also be set by writing a 1 to it. Resetting this bit to 0 allows the MFUNC4
and MFUNC1 terminals to be used for alternate functions.
0 = Serial bus interface not detected
1 = Serial bus interface detected
2
SBTEST
RW
Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes.
0 = Serial bus clock at normal operating frequency,
1 = Serial bus clock frequency increased for test purposes
100 kHz (default)
1
REQ_ERR
RC
Requested serial bus access error. Bit 1 indicates when a data error occurs on the serial interface during
a requested cycle and may be set due to a missing acknowledge. Bit 1 is cleared by a writeback of 1.
0 = No error detected during user-requested byte read or write cycle
1 = Data error detected during user-requested byte read or write cycle
0
ROM_ERR
RC
EEPROM data error status. Bit 0 indicates when a data error occurs on the serial interface during the
auto-load from the serial bus EEPROM and may be set due to a missing acknowledge. Bit 0 is also set on
invalid EEPROM data formats. See Section NO TAG,
Serial Bus EEPROM Application
, for details on
EEPROM data format. Bit 0 is cleared by a writeback of 1.
0 = No error detected during auto-load from serial bus EEPROM
1 = Data error detected during auto-load from serial bus EEPROM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCI1620PDV | Controller Miscellaneous - Datasheet Reference |
| PCI2050A | 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge |
| PCI2050GHK | BUS CONTROLLER |
| PCI2050PDV | BUS CONTROLLER |
| PCI9054AB50BI | Interface IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI1620PDV | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PC Card Flash & Smart Card Cntrlr RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI-1620U | 制造商:ADVANTECH 制造商全稱:Advantech Co., Ltd. 功能描述:8-port RS-232 PCI Communication Card, with Surge Protection |
| PCI1620ZHK | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PC Card Flash & Smart Card Cntrlr RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI-1622A-BE | 制造商:Advantech Co Ltd 功能描述:8PORT RS-422/485 PCI COM CARD - Trays 制造商:Advantech Co Ltd 功能描述:8-port RS-422/485 UPCI COMM card |
| PCI-1622CU | 制造商:ADVANTECH 制造商全稱:Advantech Co., Ltd. 功能描述:8-port RS-422/485 Universal PCI Communication Card with Isolation & EFT Protection |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。