3
–
3
Smart Cards contain eight contacts, however two of the contacts are reserved for future use and are not included
in the UltraMedia interface. Smarts Cards can be either 5-V or 3-V cards; however, all 3-V cards are designed to work
also at 5 V.
The primary use of Smart Cards is in security-related applications. They are also used in credit cards, debit systems,
and identification systems.
3.2
I/O Characteristics
Figure 3
–
2 shows a 3-state bidirectional buffer illustration for reference. Section 8.2,
Recommended Operating
Conditions
, provides the electrical characteristics of the inputs and outputs. The PCI1620 meets the ac specifications
of the
PC Card Standard
and the
PCI Local Bus Specification
.
Tied for Open Drain
OE
Pad
VCCP
Figure 3
–
2. 3-State Bidirectional Buffer
3.3
Clamping Voltages
The PCI bus supports either 3.3-V or 5-V signaling. The PC Card/CardBus sockets are also capable of supporting
3.3-V or 5-V cards. The PCI1620 meets these various signaling requirements through the use of 3.3-V I/O buffers
that are 5-V tolerant. These buffers output a 3.3-V signal level and can receive either 3.3-V or 5-V signals on their
inputs. In addition, there are clamping diodes as shown in Figure 3
–
2 that limit the overshoot of the signal. The
PCI1620 has three clamping-voltage terminals that should be connected to match whatever external environment
the PCI1620 is interfaced with, 3.3 V or 5 V.
The PCI bus I/O terminals use the V
CCP
terminal. If a system designer desires a 5-V PCI bus, then V
CCP
can be
connected to a 5-V power supply. Each PC Card/CardBus socket has its own clamping rail input, V
CCA
for socket
A and V
CCB
for socket B. By connecting V
CCA
to the voltage supply output from the external TPS222x power switch
to socket A, and V
CCB
to the voltage supply for socket B, the PCI1620 has the correct clamping-rail voltage for the
card signaling levels of both PC Card/CardBus cards.
3.4
Peripheral Component Interconnect (PCI) Interface
This section describes the PCI interface of the PCI1620, and how the device responds to and participates in PCI bus
cycles. The PCI1620 provides all required signals for PCI master/slave devices and may operate in either 5-V or 3.3-V
PCI signaling environments by connecting the V
CCP
terminals to the desired signaling level.
3.4.1
PCI Bus Lock (LOCK)
The bus locking protocol defined in the PCI specification is not highly recommended, but is provided on the PCI1620
as an additional compatibility feature. The use of LOCK is only supported by PCI-to-CardBus bridges in the
downstream direction (away from the processor).
The PCI1620 supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus
bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential
deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target
supports delayed transactions and blocks access as the target until it completes a delayed read. This target
characteristic is prohibited by the
PCI Local Bus Specification
revision 2.2, and the issue is resolved by the PCI master
using LOCK.