參數(shù)資料
型號(hào)： PCI1620GHK
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 139/164頁
文件大小： 720K
代理商： PCI1620GHK
6
–
7
6.5
Socket Control Register
This register provides control of the voltages applied to the socket V
PP
and V
CC
. The PCI1620 ensures that the socket
is powered up only at acceptable voltages when a CardBus card is inserted. See Table 6
–
6 for a complete description
of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Socket control
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Socket control
Type
R
R
R
R
R
R
RW
R
RW
RW
RW
RW
R
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Socket control
CardBus Socket Address + 10h
Read-only, Read/Write
0000 0000h
Table 6
–
6. Socket Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
31
–
12
RSVD
R
These bits return 0s when read.
11
ZV_ACTIVITY
R
This bit returns 0 when the ZVEN bits (bit 0) for both sockets are 0 (disabled). If either ZVEN bit is
set to 1, the ZV_ACTIVITY bit returns 1.
10
STANDARDZVREG
R
Standardized zoomed video register model supported. Because PCI1620 supports this register
model, this bit is hardwired to 1.
9
ZVEN
RW
Zoomed video enable. This bit enables zoomed video for the socket.
8
RSVD
R
These bits return 0s when read.
7
STOPCLK
RW
This bit controls how the CardBus clock run state machine decides when to stop the CardBus clock
to the CardBus card:
0 = The CardBus CLKRUN protocol can only attempt to stop/slow the CaredBus clock if the
sockethas been idle for 8 clocks and the PCI CLKRUN protocol is preparing to stop/slow the
PCI bus clock.
1 = The CardBus CLKRUN protocol can only attempt to stop/slow the CaredBus clock if the
sockethas been idle for 8 clocks, regardless of the state of the PCI CLKRUN signal.
6
–
4
VCCCTRL
RW
VCC control. These bits are used to request card VCC changes.
000 = Request power off (default)
001 = Reserved
010 = Request VCC = 5 V
011 = Request VCC = 3.3 V
100 = Request VCC = X.X V
101 = Request VCC = Y.Y V
110 = Reserved
111 = Reserved
3
RSVD
R
This bit returns 0 when read.
相關(guān)PDF資料
PDF描述
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
PCI9054AB50BI Interface IC
相關(guān)代理商/技術(shù)參數(shù)
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