參數(shù)資料
型號(hào)： PCI1620GHK
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 123/164頁
文件大小： 720K
代理商： PCI1620GHK
5
–
17
5.14 ExCA Memory Windows 0
–
4 Start-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23
–
A20 of the start address. In addition, the memory
window data width and wait states are set in this register. See Table 5
–
11 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Name
ExCA memory windows 0
–
4 start-address high-byte
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
Register:
Offset:
ExCA memory window 0 start-address high-byte
CardBus Socket Address + 811h:
Card A ExCA Offset 11h
Card B ExCA Offset 51h
Register:
Offset:
ExCA memory window 1 start-address high-byte
CardBus Socket Address + 819h:
Card A ExCA Offset 19h
Card B ExCA Offset 59h
Register:
Offset:
ExCA memory window 2 start-address high-byte
CardBus Socket Address + 821h:
Card A ExCA Offset 21h
Card B ExCA Offset 61h
Register:
Offset:
ExCA memory window 3 start-address high-byte
CardBus Socket Address + 829h:
Card A ExCA Offset 29h
Card B ExCA Offset 69h
Register:
Offset:
ExCA memory window 4 start-address high-byte
CardBus Socket Address + 831h:
Card A ExCA Offset 31h
Card B ExCA Offset 71h
Type:
Default:
Read/Write
00h
Table 5
–
11. ExCA Memory Windows 0
–
4 Start-Address High-Byte Registers Description
BIT
SIGNAL
TYPE
FUNCTION
7
DATASIZE
RW
This bit controls the memory window data width. This bit is encoded as:
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
6
ZEROWAIT
RW
Zero wait-state. This bit controls the memory window wait state for 8- and 16-bit accesses. This wait-state
timing emulates the ISA wait state used by the 82365SL-DF. This bit is encoded as:
0 = 8- and 16-bit cycles have standard length (default).
1 = 8-bit cycles reduced to equivalent of three ISA cycles
16-bit cycles reduced to the equivalent of two ISA cycles
5
–
4
SCRATCH
RW
Scratch pad bits. These bits have no effect on memory window operation.
3
–
0
STAHN
RW
Start address high-nibble. These bits represent the upper address bits A23
–
A20 of the memory window
start address.
相關(guān)PDF資料
PDF描述
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
PCI9054AB50BI Interface IC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCI1620PDV 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PC Card Flash & Smart Card Cntrlr RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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PCI1620ZHK 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PC Card Flash & Smart Card Cntrlr RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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