參數(shù)資料
型號： PCI1620GHK
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 61/164頁
文件大小： 720K
代理商： PCI1620GHK
3
–
19
bit 2 (IFCMODE) in the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20), and defaults to
the flag-cleared-on-read method.
The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event
register (see Section 6.1). Although some of the functionality is shared between the CardBus registers and the ExCA
registers, software should not program the chip through both register sets when a CardBus card is functioning.
3.6.3
Using Parallel IRQ Interrupts
The seven multifunction terminals, MFUNC6
–
MFUNC0, implemented in the PCI1620 can be routed to obtain a
subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use the parallel
ISA-type IRQ interrupt signaling, software must program the device control register (PCI offset 92h, see
Section 4.41), to select the parallel IRQ signaling scheme. See Section 4.38,
Multifunction Routing Register
, for
details on configuring the multifunction terminals.
A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement
is dictated by certain card and socket-services software. The INTA requirement calls for routing the MFUNC0 terminal
for INTA signaling. The INTRTIE bit is used, in this case, to route socket B interrupt events to INTA. This leaves (at
a maximum) six different IRQs to support legacy 16-bit PC Card functions.
As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ10, IRQ11,
and IRQ15. The multifunction routing register must be programmed to a value of 0FBA 5432h. This value routes the
MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 3
–
10. Not shown is
that INTA must also be routed to the programmable interrupt controller (PIC), or to some circuitry that provides parallel
PCI interrupts to the host.
PCI1620
PIC
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
IRQ3
IRQ4
IRQ5
IRQ11
IRQ10
IRQ15
Figure 3
–
10. IRQ Implementation
Power-on software is responsible for programming the multifunction routing register to reflect the IRQ configuration
of a system implementing the PCI1620. The multifunction routing register is shared between the two PCI1620
functions, and only one write to function 0 or 1 is necessary to configure the MFUNC6
–
MFUNC0 signals. Writing to
function 0 only is recommended. See Section 4.38,
Multifunction Routing Register
,
for details on configuring the
multifunction terminals.
The parallel ISA-type IRQ signaling from the MFUNC6
–
MFUNC0 terminals is compatible with the input signal
requirements of the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs.
Design constraints may demand more MFUNC6
–
MFUNC0 IRQ terminals than the PCI1620 makes available.
3.6.4
Using Parallel PCI Interrupts
Parallel PCI interrupts are available when exclusively in parallel PCI interrupt/parallel ISA IRQ signaling mode, and
when only IRQs are serialized with the IRQSER protocol. Both INTA and INTB can be routed to MFUNC terminals
(MFUNC0 and MFUNC1). However, interrupts of both socket functions can be routed to INTA (MFUNC0) if bit 29
(INTRTIE) is set in the system control register (PCI offset 80h, see Section 4.31).
The INTRTIE bit affects the read-only value provided through accesses to the interrupt pin register (PCI offset 3Dh,
see Section 4.24). When the INTRTIE bit is set, both functions return a value of 01h on reads from the interrupt pin
register for both parallel and serial PCI interrupts. Table 3
–
13 summarizes the interrupt signaling modes.
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