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參數(shù)資料
| 型號： | MT90503AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | CLIP, STRAIN RELIEF, 50WAY; For use with:820 Series Tripolarized Wiremount Sockets; Ways, No. of:50; Material:Metal; Connector type:Strain Relief RoHS Compliant: Yes |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA503 |
| 封裝： | 40 X 40 MM, 2.33 MM HEIGHT, PLASTIC, MS-034, BGA-503 |
| 文件頁數(shù)： | 74/233頁 |
| 文件大?。?/td> | 1341K |
| 代理商： | MT90503AG |
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MT90503
Data Sheet
74
Zarlink Semiconductor Inc.
Memory containing the control structures is divided into 8 KB blocks. Zero or more control structures can exist in a
block. Control structures must be fully contained in a single block. The pointers Current Entry and Last Entry are
relative to the 8 KB block boundary in which their structure resides.
The Buffer Size (BS) field indicates the size of the Receive Circular Buffers. Though the Buffer Size is indicated in
words, the received data occupies only the lower byte of each word; the data to be transmitted occupies the upper
bytes. Selection of size: 128, 256, 512, or 1024 words, depends on the amount of available memory and on the
CDV for the VC. The receive half of the buffer must be capable of holding twice the maximum CDV (peak CDV) plus
the packetisation size of the cells in the VC plus two additional bytes. Additional space must be added if E1 or T1
formats are employed (the buffer must be twice as big for E1 and a 4/3 of the size for T1). To convert the maximum
CDV from ms into bytes, a data rate of 8000 bytes/s must be applied. The packetisation size is defined as the
maximum number of bytes a channel can contain in a single cell of the VC.
To find the maximum CDV supported by the buffer, the value of the "Max Used Bytes In Circular Buffer" field must
be divided by two and multiplied by 125
μ
s/byte. Because a larger buffer will cause more delay through the
RX_SAR, the choice of the value of "Max Used Bytes In Circular Buffer" must be made as a compromise between
the CDV supported and the delay inserted by the RX_SAR. In the T1/E1 multiframe mode, the value of "Max Used
Bytes In Circular Buffer" must be an integer number of frames and is counted in a multiframe/frame fashion. The
rx_sar_wr
ite_pnt
RX_SAR write
pointer
+A/b15:b4
This is a pointer to the location where the next byte will be
written in each TX/RX Circular Buffer. It is common to all
TX/RX Circular buffers controlled by the RX_SAR Control
Structure.
In the E1/T1 mode, this field is divided in multiframe [6:0]
and frame[4:0]. Only the lower part of the field is used to
point to the TX/RX Circular Buffer.
This bit must be reset by software before enabling the VC in
the LUT. The bit is set by hardware after receiving the first
cell.
Last received AAL1 sequence number.
Second-last received AAL1 sequence number.
I
Structure
Initialised Bit
+A/b3
Last Seq
2
nd
Last
Seq
Slip Free
rx_sar_wr
ite_pnt
Received
Cell
Counter
Last Seq
2
nd
Last Seq
+A/b2:b0
+C/b2:b0
Slip-free
RX_SAR write
pointer
Received Cell
Counter
+10/b15:b4
The Slip-free rx_sar_write_pnt is the same as the
rx_sar_write_pnt except that slips (overruns and underruns)
do not affect its value.
A 32-bit free running cell counter used for monitoring activity
on a VC and for statistical purposes.
+12/b15:b0
+14/b15:b0
This field can be initialised to '0' by software.
When this bit is high the channel is active. When this bit is
reset, all received bytes on the channel are discarded.
This field is a pointer to the TX/RX Circular Buffer associated
with this channel. "0000 0000" will be appended to this field
as the LSBs to form a 22-bit address in external data
memory.
V
TDM Channel
Valid
Channel N's
TX/RX
Circular Buffer
Pointer
+16 to end/b15
Channel
N's
TX/RX
Circular
Buffer
Pointer
+16 to
end/b13:b0
Field
Name of Field
Byte Address
Offset/Bits Used
Description of Field
Table 23 - Description of the Fields for the RX_SAR Structure (continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520 | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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