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參數(shù)資料
| 型號： | MT90503AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | CLIP, STRAIN RELIEF, 50WAY; For use with:820 Series Tripolarized Wiremount Sockets; Ways, No. of:50; Material:Metal; Connector type:Strain Relief RoHS Compliant: Yes |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA503 |
| 封裝： | 40 X 40 MM, 2.33 MM HEIGHT, PLASTIC, MS-034, BGA-503 |
| 文件頁數(shù)： | 63/233頁 |
| 文件大?。?/td> | 1341K |
| 代理商： | MT90503AG |
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MT90503
Data Sheet
63
Zarlink Semiconductor Inc.
with the mapping of the transmit event scheduler. Despite this error, the MT90503 will continue with its operations,
however, some cells may be lost.
4.3.3.1 Percent of Bandwidth Register
The TX_SAR incorporates a Percent of Bandwidth
register (0510h), which indicates the maximum number of mclk
cycles utilised by the TX_SAR process per frame. The Percent of Bandwidth register counts the number of mclk
cycles from the time that a frame is received, to the time that all the entries for that frame in the schedulers have
been completely handled. This value will be compared to the current maximum value obtained by the TX_SAR
process. If the most current value is higher, it is retained and written into the Percent of Bandwidth register. The
value in the Percent of Bandwidth register can be cleared by the software. If the TX_SAR takes more than 125
μ
s to
assemble the cells of a particular frame, the Percent of Bandwidth register’s value will be greater than the number
of mclk cycles in the 125
μ
s time frame.
4.3.3.2 Distribution of Events by Software
The events in the transmit event scheduler need to be distributed as evenly as possible. For example, an “AAL1
with pointer” 3-channel VC has three events per 46.875 frames. These events must be spaced out with a distance
of 15 or 16 frames between events to prevent irregular data distribution resulting in transmission latency and/or
data integrity problems. Consequently, a scheduler 8 * 46.875 = 375 frames in length containing 24 events is
required to map the three events per 46.875 frames evenly. The mapping of this information is accomplished by
external software.
One of the key features of the transmit event schedulers is their programmable length. Since different cells require
different sizes of schedulers, the schedulers are capable of handling any scheduler length from 1 to 2048 frames.
Refer to Table 21 for examples of transmit event scheduler sizes.
4.3.4 Mapping of the Transmit Event Scheduler
With the “AAL1 with pointer”, the format for the mapping of the transmit event scheduler is asymmetric. The “AAL1
with pointer” format expects a cell every 46.875 frames per channel, a transmit event scheduler with 47 frames that
skips the last frame one turn out of eight is required. The MT90503 overcomes this difficulty by creating an
extended transmit event scheduler of 375 frames, which is 8 * 46.875. Therefore, the irregularity of the transmit
event scheduler is corrected and events can be mapped appropriately.
Due to this multiplication, the number of events mapped in the transmit event scheduler for any VC is always a
multiple of eight. This means the first event in the transmit event scheduler is always a p-byte event and contains a
zero value pointer indicating the start of a structure.
ATM Cell Type
Number of Frames
Transmit Event Scheduler size in KB
(e.g. 32 events per frame)
CBR-AAL0
AAL1 with Pointer
AAL1 without Pointer
AAL5-VTOA/CBR-AAL0
E1 with CAS
T1 with CAS
48
375
47
240
750
1125
6*
47
5.875
30
94
141
*Note: 6 KB = 32 events per frame * 48 frames per scheduler * 4 bytes per event
Table 21 - Examples of typical Transmit Event Scheduler Sizes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520 | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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