- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359234 > MT90503AG (ZARLINK SEMICONDUCTOR INC) CLIP, STRAIN RELIEF, 50WAY; For use with:820 Series Tripolarized Wiremount Sockets; Ways, No. of:50; Material:Metal; Connector type:Strain Relief RoHS Compliant: Yes PDF資料下載
參數(shù)資料
| 型號： | MT90503AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | CLIP, STRAIN RELIEF, 50WAY; For use with:820 Series Tripolarized Wiremount Sockets; Ways, No. of:50; Material:Metal; Connector type:Strain Relief RoHS Compliant: Yes |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA503 |
| 封裝： | 40 X 40 MM, 2.33 MM HEIGHT, PLASTIC, MS-034, BGA-503 |
| 文件頁數(shù)： | 40/233頁 |
| 文件大?。?/td> | 1341K |
| 代理商： | MT90503AG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁
MT90503
Data Sheet
40
Zarlink Semiconductor Inc.
4.2 TDM Module
The general architecture of the TDM bus consists of three main elements.
The TDM bus interface which is coupled directly to the bus pins and manages the timing requirements of the
H.100/H.110 interface.
The datapath management for transporting the bytes from the TDM bus to the circular buffers (located in the
external data memory).
The TDM clocking mechanism, this enables the MT90503 to be H.100/H.110 bus master capable and
communicates with the clock recovery module.
4.2.1 TDM Bus Interface
The MT90503 TDM Module interfaces with all 32 data streams of the H.100/H.110 bus. The maximum data rate of
8.192 Mbps determines the total bus capacity of 4096 TDM TSST. The MT90503 can process up to: 2048
transmitting TDM TSST and 2048 receiving TDM TSST within one frame of 125
μ
s.
One less TDM channel is carried for each CAS channel that is desired. If all TDM channels have CAS, then 1024
transmit and 1024 receive channels is the limit. The MT90503 can drive out data on any particular TSST (Time
Slot/Stream), or read in data from any particular TSST.
Each individual time slot or DS
0
on the H.1x0 bus is assigned by a unique TSST number, based on the following
equation:
The timeslot ranges from 0 to 31 for 2MHz streams, from 0 to 63 for 4MHz streams, or from 0 to 127 for 8MHz
streams.
The 16 lowest data streams are capable of running at a data rate lower than 8.192 MHz. The streams are grouped
in fours and each quartet must run at the same data rate. Streams [3:0], [7:4], [11:8] and [15:12] can each run at
2.048, 4.096 or 8.192 MHz as a group. This allows backward compatibility with older, slower TDM buses. In the
reduced rate, the data is still latched using the CT_C8_A or _B clock-edge, but using every second or every fourth
clock-edge. The streams numbered [31:16] must always run at 8.192 MHz.
The TDM bus can also be configured to use only 4, 8, or 16 streams. This configuration requires less processing of
TDM bytes and, also allows a reduced mclk speed. The 4-stream mode is useful for conducting tests, while the
16-stream mode allows mclk speed to be cut in half while still allowing half the bandwidth of a full H.100/H.110 bus.
When the H.100/H.110 bus is carrying CAS signalling bits, every even stream carries regular TDM data bytes, and
is associated with an odd stream that carries CAS bits and the indication of the beginning of the multiframe. For
TSSTs that are input to the MT90503, the multiframing is provided by the framer. For TSSTs that are generated by
the MT90503, the output multiframing is provided by the MT90503; there is one multiframe which is common to all
the T1 channel signals and one multiframe which is common to all the E1 channel signals. On the input, the
multiframing is independent for each TSST and the MT90503 synchronises all of them to its multiframe.
TSST =
timeslot * 32 + stream
(timeslot * 2+1) * 32 + stream
(timeslot * 4+3) * 32 + stream
for 8MHz streams
for 4MHz streams
for 2MHz streams
相關PDF資料 |
PDF描述 |
|---|---|
| MT90520 | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
發(fā)布緊急采購，3分鐘左右您將得到回復。