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參數(shù)資料
| 型號(hào)： | MT90503AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | CLIP, STRAIN RELIEF, 50WAY; For use with:820 Series Tripolarized Wiremount Sockets; Ways, No. of:50; Material:Metal; Connector type:Strain Relief RoHS Compliant: Yes |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA503 |
| 封裝： | 40 X 40 MM, 2.33 MM HEIGHT, PLASTIC, MS-034, BGA-503 |
| 文件頁(yè)數(shù)： | 231/233頁(yè) |
| 文件大?。?/td> | 1341K |
| 代理商： | MT90503AG |
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MT90503
Data Sheet
231
Zarlink Semiconductor Inc.
IE
:
I
nterrupt
E
nable. This is a register bit that enables a status event to generate an interrupt. This bit is always
active-high.
ISR: I
nterrupt
S
ervice
R
outine
JTAG: J
oint
T
est
A
ction
G
roup.
LUT: L
ook-
U
p
T
able. In the UTOPIA module of the MT90503, the LUT is used to associate the data from received
cells with the proper TDM output channels. The LUT is contained in the external memory.
MFS
:
M
ulti-
F
rame
S
upport. The MT90503 is capable of supporting the multi-frame standards of E1 and T1.
MVIP: M
ulti-
V
endor
I
ntegration
P
rotocol. MVIP is a standard for transmitting data on a TDM bus.
NNI: N
etwork-
N
ode
I
nterface. NNI ATM cells do not have a GFC nibble, instead having an extra nibble of VPI.
OAM: O
perations
A
dministration and
M
aintenance. MSB within the PTI field of the ATM cell header which indicates
if the ATM cell carries management information such as fault indications.
OC-3: O
ptical
C
arrier level-
3
. A Sonet channel that carries a bandwidth of 155.55 Mbps.
OC-12: O
ptical
C
arrier level-
12
. A Sonet channel that carries a bandwidth of 622.08 Mbps.
PC
:
P
rocess
C
ontrol bit. This is a register bit type that is written to ‘1’ to initiate a hardware process. When the
process completes, the hardware clears the bit.
PCM: P
ulse
C
ode
M
odulation. PCM is the basic method of encoding an analog voice signal into digital form.
PHY: PHY
sical layer. The bottom layer of the ATM Reference Model, it provides ATM cell transmission over the
physical interfaces that interconnect the various ATM devices.
PLL: P
hase
L
ock
L
oop. A phase lock loop is a component that generates an output clock by synchronising itself to
an input clock. PLLs are often used to multiply the frequency of clocks.
PTI: P
ayload
T
ype
I
dentifier. The PTI field is a 3-bit header field that encodes various cell management information.
Bit 2 (MSB) indicates OAM information or user data, bit 1 is Explicit Forward Congestion Control Indication (whether
the cell may have been delayed by network congestion -- never examined by the MT90503) and bit 0 (LSB)
indicates that a CBR-AAL5 cell is the final cell in a frame.
PUL
:
PUL
se bit. This is a register bit that is written to ‘1’ to indicate an event to the hardware. This bit is always read
at ‘0’.
RAM: R
andom
A
ccess
M
emory. RAM is the main memory in the computer. It is called “random” because any
random address can be accessed in an equal amount of time.
RO: R
ead
O
nly. This serves to define registers that cannot be written to by the CPU.
ROL: R
ead
O
nly
L
atch. This defines status bits. Status bits cannot be written to ‘1’ by the CPU; however, once the
status bit is set, the CPU can clear it by writing a ‘0’ over it.
RW: R
ead
W
rite. This type of register bit will be readable and writeable by the CPU.
SAR: S
egmentation
A
nd
R
eassembly. Method of partitioning, at the source, frames into ATM cells and
reassembling, at the destination, these cells back into information frames; lower sublayer of the AAL which inserts
data from the information frames into cells and then adds the required header, trailer, and/or padding bytes to
create 48-byte payloads to be transmitted to the ATM layer.
SCSA
: Signal Computing System Architecture
SRTS: S
ynchronous
R
esidual
T
ime
S
tamp. SRTS is a clock recovery technique, which transmits timing information
over the network to allow the source clock to be reconstructed at the other end. SRTS is sent in a 4-bit value
transmitted over 8 AAL1 cells.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520 | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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