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參數(shù)資料
| 型號(hào)： | MT90503AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | CLIP, STRAIN RELIEF, 50WAY; For use with:820 Series Tripolarized Wiremount Sockets; Ways, No. of:50; Material:Metal; Connector type:Strain Relief RoHS Compliant: Yes |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA503 |
| 封裝： | 40 X 40 MM, 2.33 MM HEIGHT, PLASTIC, MS-034, BGA-503 |
| 文件頁(yè)數(shù)： | 209/233頁(yè) |
| 文件大小： | 1341K |
| 代理商： | MT90503AG |
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MT90503
Data Sheet
209
Zarlink Semiconductor Inc.
8.1.1 Precautions During Power Sequencing
Latch-up is not a concern during power sequencing. The only requirement for sequencing 3.3 V and 5 V supplies
during power up is that the MT90503 be either held in reset until the rails are stable or have its global_tri_state pin
held low (tristate). However, to minimise over-voltage stress during system start-up, the 3.3 V supply applied to the
MT90503 should be brought to a level of at least V
DD
= 3.0 V before a signal line is driven to a level greater than or
equal to 3.3 V. This practice can be implemented either by ensuring that the 3.3 V power turns on simultaneously
with or before the system 5 V supply turns on, or by ensuring that all 5 V signals are held to a logic LOW state
during the time that V
DD
< 3.0 V. This condition is also met also if the MT90503 is held in reset until V
DD
reaches
3.0 V.
Regardless of the method chosen to limit over-voltage stress during power up, exposure must be limited to no more
than + 6.5 V input voltage (V
IN
). The global_tri_state pin of the MT90503 can be asserted low on power-up to
prevent bus contention.
8.1.2 Precautions During Power Failure
Latch-up is not a concern in power failure mode. Although extended exposure of the MT90503 to 5 V signals during
3.3 V supply power failure is not recommended, there are no restrictions as long as V
IN
does not exceed the
absolute maximum rating of 6.5 V. To minimise over-voltage stress during a 3.3 V power supply failure, the designer
should either link the power supplies to prevent this condition or ensure that all 5 V signals connected to the
MT90503 are held in a logic LOW state until the 5 V supply is deactivated.
8.1.3 Pull-ups
Pull-ups from the 5 V rail to 3.3 V (5 V tolerant) outputs of the MT90503 can cause reverse leakage currents into
those 3.3V outputs when they are active HIGH. (No significant reverse current is present during the high
impedance state.) If the application can put the MT90503 in a state where MCLK is stopped, and a large number of
3.3 V output buffers are held in a static HIGH state, current can flow from the 5 V rail to the 3.3 V rail. If this
MCLK-stopped state can not be avoided, the user should determine if the total MT90503 reverse current will have a
negative impact on the system 3.3 V power supply. Alternatively, the global_tri_state pin of the MT90503 can be
asserted low to put all outputs in the high impedance state.
8.2 H.110 Diode Clamp Rail
As the MT90503 has a diode clamp to the 5 V rail, the diode clamp must be no more than 0.7 V below V
DD
when
the pin is not tristated. This can be accomplished by asserting the global_tri_state pin low or by keeping the
MT90503 in reset until all rails are stable.
21
3.3V output LOW current (12
mA buffer)
I
OL
12.0
mA
V
OL
= 0.4 V
22
Junction-to-Ambient Thermal
Resistance
θ
J-A
14.225
°
C/W
0 cfm air flow
(natural convection
airflow only)
b. T
= 0
°
C to 70
°
C; V
= 3.3V
±
5%
Voltage measurements are with respect to ground (V
SS
) unless otherwise stated.
DC Characteristics (continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520 | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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